公开(公告)号：US20070298557A1

公开(公告)日：2007-12-27

申请号：US11607326

申请日：2006-12-01

申请人： Chun-Feng Nieh ,  Keh-Chiang Ku ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee

发明人： Chun-Feng Nieh ,  Keh-Chiang Ku ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee

IPC分类号： H01L21/8234

CPC分类号： H01L29/1083 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a stressor in the semiconductor substrate adjacent to an edge of the gate electrode; and tilt implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在栅极电介质上形成栅电极; 在所述半导体衬底中形成与所述栅电极的边缘相邻的应力源; 并且在形成应力器的步骤之后倾斜注入杂质。 杂质优选选自基本上由IV族元素，惰性元素及其组合组成的组。

公开(公告)号：US07741699B2

公开(公告)日：2010-06-22

申请号：US11521660

申请日：2006-09-15

申请人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/00

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.

摘要翻译： 半导体器件包括在半导体衬底上的栅极堆叠，半导体衬底中的轻掺杂n型源极/漏极（LDD）区域并且邻近栅极堆叠，其中LDD区域包括n型杂质，重掺杂n- （N + S / D）区，其中N + S / D区包括n型杂质，半导体衬底中的非淀粉化注入（PAI）区，其中PAI 区域包括端部范围（EOR）区域和半导体衬底中的间隙阻挡区域，其中间隙阻挡区域的深度大于LDD区域的深度但小于EOR区域的深度。

公开(公告)号：US20080160709A1

公开(公告)日：2008-07-03

申请号：US11648371

申请日：2006-12-29

申请人： Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ting Wang ,  Hsun Chang

发明人： Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ting Wang ,  Hsun Chang

IPC分类号： H01L21/336

CPC分类号： H01L21/268 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a source/drain region adjacent the gate dielectric and the gate electrode; forming an absorption-capping layer over the source/drain region and the gate electrode; performing an activation by applying a high-energy light to the absorption-capping layer; and removing the absorption-capping layer.

摘要翻译： 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在栅极电介质上形成栅电极; 形成邻近所述栅极电介质和所述栅电极的源极/漏极区域; 在源极/漏极区域和栅极电极上形成吸收覆盖层; 通过向吸收覆盖层施加高能量光来进行激活; 并去除吸收层。

公开(公告)号：US20070284615A1

公开(公告)日：2007-12-13

申请号：US11521660

申请日：2006-09-15

申请人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/739

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.

摘要翻译： 半导体器件包括在半导体衬底上的栅极堆叠，半导体衬底中的轻掺杂n型源极/漏极（LDD）区域并且邻近栅极堆叠，其中LDD区域包括n型杂质，重掺杂n- （N + S / D）区，其中N + S / D区包括n型杂质，半导体衬底中的非淀粉化注入（PAI）区，其中PAI 区域包括端部范围（EOR）区域和半导体衬底中的间隙阻挡区域，其中间隙阻挡区域的深度大于LDD区域的深度但小于EOR区域的深度。

公开(公告)号：US20080242039A1

公开(公告)日：2008-10-02

申请号：US11690869

申请日：2007-03-26

申请人： Keh-Chiang Ku ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Hsun Chang ,  Li-Ting Wang ,  Chih-Chiang Wang ,  Tze-Liang Lee

发明人： Keh-Chiang Ku ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Hsun Chang ,  Li-Ting Wang ,  Chih-Chiang Wang ,  Tze-Liang Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/2686 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823878

摘要： A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds.

摘要翻译： 增加掺杂剂激活而不会受到额外的掺杂剂扩散的方法包括在半导体衬底中形成浅掺杂的和轻掺杂的源极/漏极扩展区，在源极/漏极延伸区上执行第一退火工艺，形成深和重掺杂的源/ 漏极区域，并且在源极/漏极区域上执行第二退火处理。 第一退火工艺是在约1毫秒至3毫秒之间的时间内执行的闪光退火工艺，第二退火工艺是在约1秒至30秒之间进行的快速热退火工艺。

公开(公告)号：US07494857B2

公开(公告)日：2009-02-24

申请号：US11648371

申请日：2006-12-29

申请人： Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ting Wang ,  Hsun Chang

发明人： Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ting Wang ,  Hsun Chang

IPC分类号： H01L21/336 ,  H01L21/461

CPC分类号： H01L21/268 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a source/drain region adjacent the gate dielectric and the gate electrode; forming an absorption-capping layer over the source/drain region and the gate electrode; performing an activation by applying a high-energy light to the absorption-capping layer; and removing the absorption-capping layer.

摘要翻译： 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在栅极电介质上形成栅电极; 形成与所述栅极电介质和所述栅电极相邻的源极/漏极区域; 在源极/漏极区域和栅极电极上形成吸收覆盖层; 通过向吸收覆盖层施加高能量光来进行激活; 并去除吸收层。

公开(公告)号：US08273633B2

公开(公告)日：2012-09-25

申请号：US11690869

申请日：2007-03-26

申请人： Keh-Chiang Kuo ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Hsun Chang ,  Li-Ting Wang ,  Chih-Chiang Wang ,  Tze-Liang Lee

发明人： Keh-Chiang Kuo ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Hsun Chang ,  Li-Ting Wang ,  Chih-Chiang Wang ,  Tze-Liang Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/2686 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823878

摘要： A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds.

摘要翻译： 增加掺杂剂激活而不会受到额外的掺杂剂扩散的方法包括在半导体衬底中形成浅掺杂的和轻掺杂的源极/漏极扩展区，在源极/漏极延伸区上执行第一退火工艺，形成深和重掺杂的源/ 漏极区域，并且在源极/漏极区域上执行第二退火处理。 第一退火工艺是在约1毫秒至3毫秒之间的时间内执行的闪光退火工艺，第二退火工艺是在约1秒至30秒之间进行的快速热退火工艺。

公开(公告)号：US07504292B2

公开(公告)日：2009-03-17

申请号：US11633721

申请日：2006-12-05

申请人： Keh-Chiang Ku ,  Pang-Yen Tsai ,  Chun-Feng Nieh ,  Li-Ting Wang

发明人： Keh-Chiang Ku ,  Pang-Yen Tsai ,  Chun-Feng Nieh ,  Li-Ting Wang

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L21/26513 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, and epitaxially growing a lightly-doped source/drain (LDD) region adjacent the gate stack, wherein carbon is simultaneously doped into the LDD region.

摘要翻译： 一种用于形成半导体结构的方法包括提供半导体衬底，在半导体衬底上形成栅极堆叠，以及外围生长与栅堆叠相邻的轻掺杂源极/漏极（LDD）区域，其中碳同时掺杂到LDD区域 。

公开(公告)号：US20080132019A1

公开(公告)日：2008-06-05

申请号：US11633721

申请日：2006-12-05

申请人： Keh-Chiang Ku ,  Pang-Yen Tsai ,  Chun-Feng Nieh ,  Li-Ting Wang

发明人： Keh-Chiang Ku ,  Pang-Yen Tsai ,  Chun-Feng Nieh ,  Li-Ting Wang

IPC分类号： H01L21/04

CPC分类号： H01L21/26586 ,  H01L21/26513 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, and epitaxially growing a lightly-doped source/drain (LDD) region adjacent the gate stack, wherein carbon is simultaneously doped into the LDD region.

摘要翻译： 一种用于形成半导体结构的方法包括提供半导体衬底，在半导体衬底上形成栅极堆叠，以及外围生长与栅堆叠相邻的轻掺杂源极/漏极（LDD）区域，其中碳同时掺杂到LDD区域 。

公开(公告)号：US20100105185A1

公开(公告)日：2010-04-29

申请号：US12259028

申请日：2008-10-27

申请人： Keh-Chiang Ku ,  Cheng-Lung Hung ,  Li-Ting Wang ,  Chien-Hao Chen ,  Chien-Hao Huang ,  Wenli Lin ,  Yu-Chang Lin

发明人： Keh-Chiang Ku ,  Cheng-Lung Hung ,  Li-Ting Wang ,  Chien-Hao Chen ,  Chien-Hao Huang ,  Wenli Lin ,  Yu-Chang Lin

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/28052 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28506 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.

摘要翻译： 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成栅电极层; 将碳和氮掺杂到栅电极层中; 并且在掺杂碳和氮的步骤之后，分别构图栅极电介质层和栅极电极层以形成栅极电介质和栅电极。