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1.发明授权Method and apparatus for shared multi-bank memory in a packet switching system 有权分组交换系统中共享多组存储器的方法和装置公开(公告)号：US08861515B2
公开(公告)日：2014-10-14
申请号：US10552601
申请日：2004-04-21
申请人： Chung Kuang Chin , Yaw Fann , Roy T. Myers, Jr.
发明人： Chung Kuang Chin , Yaw Fann , Roy T. Myers, Jr.
IPC分类号： H04L12/50 , H04Q11/00 , H04L12/861 , H04L12/933 , H04L12/931
CPC分类号： H04L49/201 , H04L49/101 , H04L49/103 , H04L49/351 , H04L49/90
摘要： Generally, a method and apparatus are disclosed that store sequential data units of a data packet received at an input port in contiguous banks of a buffer in a shared memory, thereby obviating any need for storing linkage information between data units. Data packets can extend through multiple buffers (next-buffer linkage information is much more efficient than next-data-unit linkage information). According to another aspect of the invention, buffer memory utilization can be further enhanced by storing multiple packets in a single buffer. For each buffer, a buffer usage count is stored that indicates the sum (over all packets represented in the buffer) of the number of output ports toward which each of the packets is destined.
摘要翻译： 通常，公开了存储在共享存储器中的缓冲器的连续存储体中的输入端口处接收的数据包的顺序数据单元的方法和装置，从而避免了在数据单元之间存储链接信息的任何需要。 数据包可以通过多个缓冲区扩展（下一缓冲区链接信息比下一个数据单元链接信息更有效）。 根据本发明的另一方面，可以通过将多个分组存储在单个缓冲器中来进一步增强缓冲存储器利用。 对于每个缓冲器，存储缓冲器使用计数，其指示每个分组到达的输出端口的数量的总和（在缓冲器中表示的所有分组上）。
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公开(公告)号：US5594702A
公开(公告)日：1997-01-14
申请号：US495867
申请日：1995-06-28
CPC分类号： G06F5/065
摘要： A multi-first-in-first-out (henceforth "multi-FIFO") memory circuit in accordance with this invention comprises: (1) a plurality of groups of storage elements, for example, each group corresponds to a first-in-first-out (FIFO) memory (2) a time multiplexed first address generator for generating address signals of a storage element from a first group that is cyclically selected from the plurality of groups by a sequencer included in the first address generator and (3) a second address generator for generating address signals of a number of successive storage elements from a second group that is selected from the plurality of groups by a signal on a group request terminal of the second address generator. In one embodiment the storage elements are part of a dualport random-access-memory (RAM), and are accessed by each of the first and second address generators using a number of pairs of pointer registers that are coupled to the address generators. Each pair of pointer registers includes a read pointer register that indicates a corresponding group's next storage element to be read and a write pointer register that indicates the group's next storage element to be written.
摘要翻译： 根据本发明的多先进先出（以下称为“多FIFO”）存储器电路包括：（1）多个存储元件组，例如每个组对应于第一存储元件， 先出（FIFO）存储器（2），时分复用第一地址发生器，用于通过包括在第一地址生成器中的定序器从第一组生成来自多个组的循环选择的存储元件的地址信号;（3） 第二地址发生器，用于通过第二地址发生器的组请求终端上的信号从多个组中选择的第二组生成多个连续存储元件的地址信号。 在一个实施例中，存储元件是双端口随机存取存储器（RAM）的一部分，并且由第一和第二地址发生器中的每一个使用耦合到地址发生器的多对指针寄存器来访问。 每对指针寄存器包括读指针寄存器，其指示相应组的下一个要读取的存储元件和指示该组下一个要写入的存储元件的写指针寄存器。
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公开(公告)号：US5740175A
公开(公告)日：1998-04-14
申请号：US538321
申请日：1995-10-03
CPC分类号： H04L49/351 , H04L49/25
摘要： A LAN network switch includes a RAM forwarding database which contains the address-to-port mappings for all the workstations or other devices connected to the switch's plurality of ports and further includes at least one CAM-cache connected to respective one or more of the switch's ports. The CAM-cache, having an access time much faster than that of the forwarding database, stores selected ones of the address-to-port mappings. When it is desired for the switch to forward a packet, the destination address is extracted and the CAM-cache is accessed and searched. If the correct mapping is contained in the CAM-cache, the packet is immediately forwarded to the destination port without accessing the much larger and slower forwarding database. Only if the CAM-cache does not contain the correct mapping is the forwarding database accessed to retrieve the correct mapping. The packet is then forwarded to the destination port, and the CAM-cache is updated with this mapping so that succeeding packets having the same destination address-to-port mapping may be forwarded to the destination port by accessing only the fast CAM-cache and, by eliminating the need to access the much slower forwarding database, increasing the forwarding speed of the switch.
摘要翻译： LAN网络交换机包括RAM转发数据库，其包含用于所有工作站或连接到交换机的多个端口的其他设备的地址对端口映射，并且还包括连接到交换机的多个端口中的一个或多个的至少一个CAM缓存 港口。 具有比转发数据库快的访问时间的CAM缓存存储所选择的地址到端口映射。 当需要转发转发数据包时，提取目的地址，并访问和搜索CAM高速缓存。 如果正确的映射包含在CAM缓存中，则数据包将立即转发到目标端口，而无需访问更大和更慢的转发数据库。 只有CAM-cache不包含正确的映射，才能访问转发数据库以检索正确的映射。 然后将数据包转发到目标端口，并且使用该映射更新CAM缓存，使得具有相同目的地地址到端口映射的后续分组可以通过仅访问快速CAM缓存而被转发到目的地端口，并且 ，通过消除访问速度较慢的转发数据库的需要，增加交换机的转发速度。
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公开(公告)号：US06185226B2
公开(公告)日：2001-02-06
申请号：US09103258
申请日：1998-06-22
申请人： Para K. Segaram , Roy T. Myers, Jr.
发明人： Para K. Segaram , Roy T. Myers, Jr.
IPC分类号： H04J308
摘要： A repeater interface controller (“RIC”) integrated circuit with integrated filters and buffer drivers is provided for use in a repeater. In one embodiment, the RIC uses two filters to filter link pulse signals and data signals for a plurality of ports. Thus, the RIC is able to concurrently provide filtered link pulses to some ports and filtered data signals to other ports. Further, because only two filters are used, the area required to implement the plurality of ports is reduced relative to conventional repeaters that use a filter for each port. In another embodiment of the present invention, a RIC includes a logic circuit and a plurality of analog multiplexers and twisted pair buffer drivers. The analog multiplexers receive signals on their input lines and select which of these signals are passed to the buffer drivers to be outputted. The logic circuit provides control signals to the analog multiplexers such that the analog multiplexers select a new input line when the signal on the new input line is approximately the same as the signal on the currently selected input line. As a result, the signal passed on to the buffer drivers remains approximately the same, thereby reducing switching noise.
摘要翻译： 具有集成滤波器和缓冲驱动器的中继器接口控制器（“RIC”）集成电路可用于中继器。 在一个实施例中，RIC使用两个滤波器来滤波多个端口的链路脉冲信号和数据信号。 因此，RIC能够同时向某些端口提供滤波的链路脉冲，并将滤波的数据信号同时提供给其他端口。 此外，由于仅使用两个滤波器，相对于使用每个端口的滤波器的常规中继器，实现多个端口所需的面积减小。 在本发明的另一实施例中，RIC包括逻辑电路和多个模拟多路复用器和双绞线缓冲器驱动器。 模拟多路复用器在其输入线路上接收信号，并选择这些信号中的哪一个传送到缓冲器驱动器以输出。 逻辑电路向模拟多路复用器提供控制信号，使得当新输入线上的信号与当前选择的输入线上的信号大致相同时，模拟多路复用器选择新的输入线。 结果，传递到缓冲器驱动器的信号保持大致相同，从而降低开关噪声。
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公开(公告)号：US5790786A
公开(公告)日：1998-08-04
申请号：US496038
申请日：1995-06-28
CPC分类号： G06F13/385
摘要： A multi-media-access-controller (henceforth "multi-MAC") in accordance with this invention includes a plurality of transmit data path circuits and a plurality of receive data path circuits that respectively transmit and receive data serially on a corresponding plurality of network buses, a single transmit data path controller and a single receive data path controller that monitor status of and control operation of the respective transmit and receive data path circuits. Use of only two data path controllers eliminates the plurality of MACs used in prior art devices and therefore results in significant savings in die area. Use of a single CRC calculator also results in savings in die area.
摘要翻译： 根据本发明的多媒体访问控制器（以下称为“多MAC”）包括多个发送数据路径电路和多个接收数据路径电路，其分别在对应的多个网络上串行地发送和接收数据 总线，单个发送数据路径控制器和监视各个发送和接收数据路径电路的状态和控制操作的单个接收数据路径控制器。 仅使用两个数据路径控制器消除了现有技术设备中使用的多个MAC，并因此导致管芯面积的显着节省。 使用单个CRC计算器也可以节省裸片面积。
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公开(公告)号：US07983287B2
公开(公告)日：2011-07-19
申请号：US12120533
申请日：2008-05-14
申请人： John T. Musacchio , Jean Walrand , Roy T. Myers, Jr. , Shyam P. Parekh , Jeonghoon Mo , Gaurav Agarwal
发明人： John T. Musacchio , Jean Walrand , Roy T. Myers, Jr. , Shyam P. Parekh , Jeonghoon Mo , Gaurav Agarwal
IPC分类号： H04L12/56
CPC分类号： H04Q3/68 , H04L49/1515 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/3072
摘要： Roughly described, a packet switching fabric contains a separate queue scheduler for each combination of an input module and a fabric output port. The schedulers may also be specific to a single class of service. Each queue scheduler schedules its packets without regard to state of other input queues and without regard to packets destined for other output ports. In an aspect, the fabric manages per-flow bandwidth utilization of output port bandwidth capacity by monitoring the same and asserting backpressure toward the queue scheduler for any thread that is exceeding its bandwidth allocation. In another aspect, a switching fabric uses leaky buckets to apply backpressure in response to overutilization of downstream port capacity by particular subflows. In another aspect, a switching fabric includes a cascaded backpressure scheme.
摘要翻译： 粗略地描述，分组交换结构包含用于输入模块和结构输出端口的每个组合的单独的队列调度器。 调度器也可能是单一类服务的特定的。 每个队列调度器调度其分组，而不考虑其他输入队列的状态，而不考虑目的地为其他输出端口的分组。 在一方面，该架构通过监视相同的方式来管理输出端口带宽容量的每流量带宽利用率，并针对超过其带宽分配的任何线程向队列调度器确定背压。 在另一方面，交换结构使用泄漏桶来响应特定子流的下游端口容量的过度利用来应用背压。 另一方面，交换结构包括级联背压方案。
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公开(公告)号：US5822325A
公开(公告)日：1998-10-13
申请号：US500298
申请日：1995-07-10
申请人： Para K. Segaram , Roy T. Myers, Jr.
发明人： Para K. Segaram , Roy T. Myers, Jr.
摘要： A repeater interface controller ("RIC") integrated circuit with integrated filters and buffer drivers is provided for use in a repeater. In one embodiment, the RIC uses two filters to filter link pulse signals and data signals for a plurality of ports. Thus, the RIC is able to concurrently provide filtered link pulses to some ports and filtered data signals to other ports. Further, because only two filters are used, the area required to implement the plurality of ports is reduced relative to conventional repeaters that use a filter for each port. In another embodiment of the present invention, a RIC includes a logic circuit and a plurality of analog multiplexers and twisted pair buffer drivers. The analog multiplexers receive signals on their input lines and select which of these signals are passed to the buffer drivers to be outputted. The logic circuit provides control signals to the analog multiplexers such that the analog multiplexers select a new input line when the signal on the new input line is approximately the same as the signal on the currently selected input line. As a result, the signal passed on to the buffer drivers remains approximately the same, thereby reducing switching noise.
摘要翻译： 具有集成滤波器和缓冲驱动器的中继器接口控制器（“RIC”）集成电路可用于中继器。 在一个实施例中，RIC使用两个滤波器来滤波多个端口的链路脉冲信号和数据信号。 因此，RIC能够同时向某些端口提供滤波的链路脉冲，并将滤波的数据信号同时提供给其他端口。 此外，由于仅使用两个滤波器，相对于使用每个端口的滤波器的常规中继器，实现多个端口所需的面积减小。 在本发明的另一实施例中，RIC包括逻辑电路和多个模拟多路复用器和双绞线缓冲器驱动器。 模拟多路复用器在其输入线路上接收信号，并选择这些信号中的哪一个传送到缓冲器驱动器以输出。 逻辑电路向模拟多路复用器提供控制信号，使得当新输入线上的信号与当前选择的输入线上的信号大致相同时，模拟多路复用器选择新的输入线。 结果，传递到缓冲器驱动器的信号保持大致相同，从而降低开关噪声。
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公开(公告)号：US07426185B1
公开(公告)日：2008-09-16
申请号：US10358678
申请日：2003-02-05
申请人： John T. Musacchio , Jean Walrand , Roy T. Myers, Jr. , Shyam P. Parekh , Jeonghoon Mo , Gaurav Agarwal
发明人： John T. Musacchio , Jean Walrand , Roy T. Myers, Jr. , Shyam P. Parekh , Jeonghoon Mo , Gaurav Agarwal
IPC分类号： G01R31/08
CPC分类号： H04Q3/68 , H04L49/1515 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/3072
摘要： Roughly described, a packet switching fabric contains a separate queue scheduler for each combination of an input module and a fabric output port. The schedulers may also be specific to a single class of service. Each queue scheduler schedules its packets without regard to state of other input queues and without regard to packets destined for other output ports. In an aspect, the fabric manages per-flow bandwidth utilization of output port bandwidth capacity by monitoring the same and asserting backpressure toward the queue scheduler for any thread that is exceeding its bandwidth allocation. In another aspect, a switching fabric uses leaky buckets to apply backpressure in response to overutilization of downstream port capacity by particular subflows. In another aspect, a switching fabric includes a cascaded backpressure scheme.
摘要翻译： 粗略地描述，分组交换结构包含用于输入模块和结构输出端口的每个组合的单独的队列调度器。 调度器也可能是单一类服务的特定的。 每个队列调度器调度其分组，而不考虑其他输入队列的状态，而不考虑目的地为其他输出端口的分组。 在一方面，该架构通过监视相同的方式来管理输出端口带宽容量的每流量带宽利用率，并针对超过其带宽分配的任何线程向队列调度器确定背压。 在另一方面，交换结构使用泄漏桶来响应特定子流的下游端口容量的过度利用来应用背压。 另一方面，交换结构包括级联背压方案。
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