公开(公告)号：US07432156B1

公开(公告)日：2008-10-07

申请号：US11409361

申请日：2006-04-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

IPC分类号： H01L21/8247

CPC分类号： H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

摘要翻译： 提供半导体存储器件及其制造方法。 根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。 蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。 掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

公开(公告)号：US07564091B2

公开(公告)日：2009-07-21

申请号：US12199692

申请日：2008-08-27

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

摘要翻译： 提供半导体存储器件及其制造方法。 根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。 蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。 掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

公开(公告)号：US20080315290A1

公开(公告)日：2008-12-25

申请号：US12199692

申请日：2008-08-27

申请人： Chungho LEE ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

发明人： Chungho LEE ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

IPC分类号： H01L29/00

CPC分类号： H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

摘要翻译： 提供半导体存储器件及其制造方法。 根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。 蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。 掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

公开(公告)号：US07666739B2

公开(公告)日：2010-02-23

申请号：US11614048

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/792

摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

摘要翻译： 提供了用于制造分离电荷存储节点半导体存储器件的方法。 根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极 。 栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。 第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构 厚度。

公开(公告)号：US08076712B2

公开(公告)日：2011-12-13

申请号：US12840165

申请日：2010-07-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且第二层结构形成在第二侧上，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US07767517B2

公开(公告)日：2010-08-03

申请号：US11613513

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L21/8242

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US20080153222A1

公开(公告)日：2008-06-26

申请号：US11614048

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/792

摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

摘要翻译： 提供了用于制造分离电荷存储节点半导体存储器件的方法。 根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极 。 栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。 第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构 厚度。

公开(公告)号：US20080149999A1

公开(公告)日：2008-06-26

申请号：US11613513

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US07696038B1

公开(公告)日：2010-04-13

申请号：US11412365

申请日：2006-04-26

申请人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Timothy Thurgate ,  Wei Zheng ,  Ashot Melik-Martirosian ,  Angela Hui ,  Chih-Yuh Yang

发明人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Timothy Thurgate ,  Wei Zheng ,  Ashot Melik-Martirosian ,  Angela Hui ,  Chih-Yuh Yang

IPC分类号： H01L21/8238

CPC分类号： H01L27/11568 ,  G11C16/3418 ,  G11C16/3427

摘要： Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.

摘要翻译： 提供了制造闪速存储器件的方法。 根据本发明的示例性实施例，一种用于制造存储器件的方法包括形成覆盖衬底的第一栅极堆叠和第二栅极堆叠。 在第一栅极堆叠和第二栅极堆叠之间的沟槽被蚀刻到衬底中。 第一杂质掺杂区域形成在沟槽下面的衬底内。

公开(公告)号：US07915123B1

公开(公告)日：2011-03-29

申请号：US11408866

申请日：2006-04-20

申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  Y10S438/954

摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

摘要翻译： 提供了一种双节点存储器件及其制造方法。 在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。 这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。 在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。 沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。 侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。 在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。