公开(公告)号：US08907829B1

公开(公告)日：2014-12-09

申请号：US13896526

申请日：2013-05-17

Applicant: Cirrus Logic, Inc.

Inventor： Ali Naderi

IPC: H03M3/00 ,  H03M1/12 ,  H03M1/80 ,  H03M1/00

CPC classification number: H03M3/496 ,  H03M1/00 ,  H03M1/12 ,  H03M1/804 ,  H03M3/30 ,  H03M3/424

Abstract: In accordance with systems and methods of the present disclosure, an input network for a delta-sigma modulator having at least one integrator stage and a feedback digital-to-analog stage, may be configured to, during a first period of a first phase of a clock signal, drive an analog feedback signal proportional to a digital feedback signal of the feedback digital-to-analog stage onto an input plate of a sampling capacitor integral to the input network. The input network may further be configured to, during a second period of the first phase of the clock signal, sample an analog input signal onto the input plates of the sampling capacitor.

Abstract translation: 根据本公开的系统和方法，用于具有至少一个积分器级和反馈数模转换级的Δ-Σ调制器的输入网络可以被配置为在第一阶段的第一阶段期间， 时钟信号，将与反馈数模转换级的数字反馈信号成比例的模拟反馈信号驱动到与输入网络集成的采样电容器的输入板上。 输入网络还可以被配置为在时钟信号的第一阶段的第二周期期间将模拟输入信号采样到采样电容器的输入板上。