Systems and methods for clock synchronization in a data acquisition system

    公开(公告)号:US10033390B2

    公开(公告)日:2018-07-24

    申请号:US14747068

    申请日:2015-06-23

    Abstract: A system may include a sampling circuit, a temperature calibration system, a phase detector, a virtual phase-locked loop, and a sample rate converter. The sampling circuit may be configured to generate a series of digitally-sampled data at a sampling frequency provided by a local clock. The temperature calibration system may be configured to determine a temperature-based timing compensation with respect to the local clock. The phase detector may be configured to estimate an error of the local clock in view of the reference clock. The virtual phase-locked loop may be configured to generate a virtual clock based on the temperature-based timing compensation and the error. The sample rate converter may be configured to generate a corrected series of digitally-sampled data in response to the virtual clock by interpolating the series of digitally-sampled data to correct for the error.

    Systems and methods of element scrambling for compensation and calibration of analog-to-digital converter feedback
    2.
    发明授权
    Systems and methods of element scrambling for compensation and calibration of analog-to-digital converter feedback 有权
    元件加扰的系统和方法用于模数转换器反馈的补偿和校准

    公开(公告)号:US09407279B2

    公开(公告)日:2016-08-02

    申请号:US14617376

    申请日:2015-02-09

    Abstract: An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal.

    Abstract translation: 装置可以包括扰频器元件,其被配置为接收输入信号并且基于输入信号生成具有多个比特的加扰温度计类似码字的信号,并且具有多个可能的量化值。 加扰器元件可以为每个可能的量化值生成加扰的温度计代码样信号的至少一个等效代码。 对于一个或多个可能的量化值中的每个,加扰器元件可以被配置为生成加扰的温度计代码样信号的多个可能的等效代码。 响应于指示加扰的温度计编码类信号的量化值的改变的输入信号,加扰器元件可以通过转换加扰的温度计代码样信号的多个比特的最小可能数来改变加扰的温度计代码样信号 信号以根据输入信号改变加扰的温度计代码样信号的量化值。

    SYSTEMS AND METHODS FOR CLOCK SYNCHRONIZATION IN A DATA ACQUISITION SYSTEM
    3.
    发明申请
    SYSTEMS AND METHODS FOR CLOCK SYNCHRONIZATION IN A DATA ACQUISITION SYSTEM 审中-公开
    数据采集​​系统中时钟同步的系统和方法

    公开(公告)号:US20150372681A1

    公开(公告)日:2015-12-24

    申请号:US14747068

    申请日:2015-06-23

    CPC classification number: H03L1/028 H03B5/32 H03L1/026 H03L7/0991

    Abstract: A system may include a sampling circuit, a temperature calibration system, a phase detector, a virtual phase-locked loop, and a sample rate converter. The sampling circuit may be configured to generate a series of digitally-sampled data at a sampling frequency provided by a local clock. The temperature calibration system may be configured to determine a temperature-based timing compensation with respect to the local clock. The phase detector may be configured to estimate an error of the local clock in view of the reference clock. The virtual phase-locked loop may be configured to generate a virtual clock based on the temperature-based timing compensation and the error. The sample rate converter may be configured to generate a corrected series of digitally-sampled data in response to the virtual clock by interpolating the series of digitally-sampled data to correct for the error.

    Abstract translation: 系统可以包括采样电路,温度校准系统,相位检测器,虚拟锁相环和采样率转换器。 采样电路可以被配置为以由本地时钟提供的采样频率生成一系列数字采样数据。 温度校准系统可以被配置为确定相对于本地时钟的基于温度的定时补偿。 相位检测器可以被配置为考虑到参考时钟来估计本地时钟的误差。 虚拟锁相环可以被配置为基于基于温度的定时补偿和误差来生成虚拟时钟。 采样率转换器可以被配置为通过内插一系列数字采样数据来校正错误来产生响应于虚拟时钟的经校正的数字采样数据序列。

    SYSTEMS AND METHODS OF ELEMENT SCRAMBLING FOR COMPENSATION AND CALIBRATION OF ANALOG-TO-DIGITAL CONVERTER FEEDBACK
    4.
    发明申请
    SYSTEMS AND METHODS OF ELEMENT SCRAMBLING FOR COMPENSATION AND CALIBRATION OF ANALOG-TO-DIGITAL CONVERTER FEEDBACK 有权
    元件数字转换器反馈补偿和校准元件的系统和方法

    公开(公告)号:US20160006448A1

    公开(公告)日:2016-01-07

    申请号:US14617376

    申请日:2015-02-09

    Abstract: An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal.

    Abstract translation: 装置可以包括扰频器元件,其被配置为接收输入信号并且基于输入信号生成具有多个比特的加扰温度计类似码字的信号,并且具有多个可能的量化值。 加扰器元件可以为每个可能的量化值生成加扰的温度计代码样信号的至少一个等效代码。 对于一个或多个可能的量化值中的每个,加扰器元件可以被配置为生成加扰的温度计代码样信号的多个可能的等效代码。 响应于指示加扰的温度计编码类信号的量化值的改变的输入信号,加扰器元件可以通过转换加扰的温度计代码样信号的多个比特的最小可能数来改变加扰的温度计代码样信号 信号以根据输入信号改变加扰的温度计代码样信号的量化值。

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