公开(公告)号：US20210066221A1

公开(公告)日：2021-03-04

申请号：US16897036

申请日：2020-06-09

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Kathryn Rose HOLLAND ,  Marc L. TARABBIA ,  Yaoyu PANG ,  Alexander BARR

IPC: H01L23/00

Abstract: A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.

公开(公告)号：US20190103490A1

公开(公告)日：2019-04-04

申请号：US15720977

申请日：2017-09-29

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Scott WARRICK ,  Justin DOUGHERTY ,  Alexander BARR ,  Christian LARSEN ,  Marc L. TARABBIA ,  Ying YING

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/76

Abstract: A dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) may include a MOSFET having a channel region, a drain, and a source, a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region.