公开(公告)号：US20210066221A1

公开(公告)日：2021-03-04

申请号：US16897036

申请日：2020-06-09

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Kathryn Rose HOLLAND ,  Marc L. TARABBIA ,  Yaoyu PANG ,  Alexander BARR

IPC: H01L23/00

Abstract: A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.

公开(公告)号：US20250107162A1

公开(公告)日：2025-03-27

申请号：US18585438

申请日：2024-02-23

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Kuen-Ting SHIU ,  Suman BANERJEE ,  Claude ORTOLLAND ,  Marc L. TARABBIA ,  Caitlin BRANDON ,  Jin TANG

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/02 ,  H01L29/08

Abstract: A semiconductor structure may include a substrate having a surface, an isolation structure formed on the surface, an active region formed on the surface adjacent to the isolation structure, a gate extended over the isolation structure and the active region, and a source region formed within the active region. The source region may include a first subregion formed adjacent to a first portion of the gate and the isolation structure, the first subregion having a first doping and a second subregion formed adjacent to a second portion of the gate, wherein the second subregion has a second doping different from the first doping.

公开(公告)号：US20250107135A1

公开(公告)日：2025-03-27

申请号：US18434993

申请日：2024-02-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Suman BANERJEE ,  Claude ORTOLLAND ,  Marc L. TARABBIA ,  Kuen-Ting SHIU ,  Jin TANG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06

Abstract: A semiconductor structure may include a substrate, an active region formed on the substrate, a gate region extended over the active region along a first direction parallel to a surface of the substrate, and a source region formed within the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction. The source region may comprise a first subregion and a second subregion such that the second subregion is between the first subregion and the gate region. The first subregion may comprise a first width along the first direction and the second subregion may comprise a second width along the first direction. The first width may be less than the second width.

公开(公告)号：US20190103490A1

公开(公告)日：2019-04-04

申请号：US15720977

申请日：2017-09-29

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Scott WARRICK ,  Justin DOUGHERTY ,  Alexander BARR ,  Christian LARSEN ,  Marc L. TARABBIA ,  Ying YING

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/76

Abstract: A dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) may include a MOSFET having a channel region, a drain, and a source, a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region.