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公开(公告)号：US11777517B2
公开(公告)日：2023-10-03
申请号：US17096582
申请日：2020-11-12
Inventor： Chandra Prakash , Bhupendra Manola , John L. Melanson
IPC: H03M3/00
Abstract: An integrated circuit having multiple switched-capacitor delta-sigma data converter circuits includes compensation for voltage reference error due to leakage current that causes reference voltage droop. The reference filter capacitor terminal voltage is maintained by periodic connection to the reference feedback capacitor(s) that are alternately connected to a voltage reference buffer, and the leakage into the reference feedback capacitor networks of disabled converter circuits causes reference voltage droop. The compensation is either determined from the number of converter circuits that are disabled, or from an error between the filter capacitor voltage and a separate voltage reference, and may be applied by adjusting a resistance selectively coupled between the voltage reference buffer output and the filter capacitor, feedback applied to the voltage reference buffer or its input source. Alternatively, or in combination, correction may be applied to the output of the active converters by digital adjustment of output values.
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公开(公告)号：US11231732B1
公开(公告)日：2022-01-25
申请号：US16922654
申请日：2020-07-07
Inventor： Chandra Prakash , Prashanth Drakshapalli
Abstract: A power managed voltage reference quickly provides accurate operation when enabled and also avoids back-charging power supply rails when disabled. When disabled, the voltage reference filter capacitor is decoupled from the voltage reference buffer and coupled to a pre-charge source having a voltage magnitude greater than the reference voltage. When the voltage reference is enabled, the capacitor is coupled to a discharge path and the voltage across the capacitor is detected to determine when to decouple the capacitor from the discharge path and couple the capacitor to the voltage reference buffer. The capacitor voltage is also detected while disabling the voltage reference. Back-charging the pre-charge supply is prevented by coupling the capacitor to the discharge path until the magnitude of the capacitor voltage is less than the lowest voltage specified for the pre-charge supply, then coupling the capacitor to the pre-charge supply to prepare for enabling the voltage reference.
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公开(公告)号：US20230308060A1
公开(公告)日：2023-09-28
申请号：US18204356
申请日：2023-05-31
Inventor： John L. Melanson , Cory J. Peterson , Chandra Prakash , Ramin Zanbaghi , Eric Kimball
CPC classification number: H03F3/2178 , H03F1/26 , H03F3/187 , H03F2200/03
Abstract: Amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include multiple driver circuits and a control circuit. The control circuit selects between actively operating selected ones of the multiple driver circuits or all of the multiple driver circuits, according to an input signal to be reproduced by one or more of the multiple amplifier driver circuits. The control circuit determines a splice point at which the control circuit selects between actively operating selected ones of the multiple driver circuits or all of the multiple driver circuits.
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公开(公告)号：US11722107B2
公开(公告)日：2023-08-08
申请号：US17589047
申请日：2022-01-31
Inventor： John L. Melanson , Cory J. Peterson , Chandra Prakash , Ramin Zanbaghi , Eric Kimball
CPC classification number: H03F3/2178 , H03F1/26 , H03F3/187 , H03F2200/03
Abstract: Class-D amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include a first H-bridge driver circuit and a second H-bridge driver circuit. The class-D amplifier circuits also include a control circuit having an input for receiving an input signal to be reproduced by the class-D amplifier circuit. The control circuit has outputs coupled to inputs of the first and second H-bridge drivers, and includes one or more modulators. The control circuit selects between actively operating a selected one of the driver circuits or both, according to the signal to be reproduced, while setting an unselected driver circuit to turn either a high-side switch or a low-side switch of the unselected one of the first driver circuit or the second driver circuit fully on for at least some cycles of the one or more modulators.
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公开(公告)号：US11190148B2
公开(公告)日：2021-11-30
申请号：US16732993
申请日：2020-01-02
Inventor： Eric Kimball , Chandra Prakash , Ramin Zanbaghi , Cory J. Peterson
Abstract: A system may include a forward signal path having a forward gain and configured to receive an input signal at an input and generate an output signal at an output as a function of the input signal, a feedback signal path having a feedback gain and coupled between the output and the input, and a control subsystem configured to operate the forward signal path and the feedback signal path in at least two modes comprising a first mode in which the forward gain is a first forward gain and the feedback gain is a first feedback gain and a second mode in which the forward gain is a second forward gain smaller than the first forward gain and the feedback gain is a second feedback gain larger than the first feedback gain. The control subsystem may cause operation in the first mode when signal content is present in the input signal and may cause operation in the second mode when signal content is absent from the input signal.
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Patent Agency Ranking
公开(公告)号：US20220011797A1
公开(公告)日：2022-01-13
申请号：US16922654
申请日：2020-07-07
Inventor： Chandra Prakash , Prashanth Drakshapalli
Abstract: A power managed voltage reference quickly provides accurate operation when enabled and also avoids back-charging power supply rails when disabled. When disabled, the voltage reference filter capacitor is decoupled from the voltage reference buffer and coupled to a pre-charge source having a voltage magnitude greater than the reference voltage. When the voltage reference is enabled, the capacitor is coupled to a discharge path and the voltage across the capacitor is detected to determine when to decouple the capacitor from the discharge path and couple the capacitor to the voltage reference buffer. The capacitor voltage is also detected while disabling the voltage reference. Back-charging the pre-charge supply is prevented by coupling the capacitor to the discharge path until the magnitude of the capacitor voltage is less than the lowest voltage specified for the pre-charge supply, then coupling the capacitor to the pre-charge supply to prepare for enabling the voltage reference.
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公开(公告)号：US11223368B1
公开(公告)日：2022-01-11
申请号：US17061939
申请日：2020-10-02
Inventor： Chandra Prakash , Saurabh Singh
IPC: H03M3/00
Abstract: A switched-capacitor delta-sigma data converter circuit includes compensation for voltage reference error that may cause non-linearity and inter-channel crosstalk. The circuit includes a voltage reference circuit, an integrator, a quantizer that quantizes the output of the integrator and a reference feedback switched-capacitor network that provides feedback charge quanta to the integrator that represents an output of the quantizer, so that the output of the quantizer, on average, represents an input signal provided to the integrator. In addition, a compensation switched-capacitor network is included for drawing dummy load charge quanta from the voltage reference output that is not provided to the integrator so that a total charge drawn from the voltage reference output when the reference feedback switched-capacitor network is coupled to the voltage reference output does not vary as the input voltage varies.
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公开(公告)号：US11489498B1
公开(公告)日：2022-11-01
申请号：US17338160
申请日：2021-06-03
Inventor： Chandra Prakash , Cory J. Peterson , Eric Kimball
Abstract: An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage. Each particular buffer of the plurality of buffers may include a buffering subcircuit configured to buffer the respective component of the differential pulse-width modulation input signal associated with the particular buffer in order to generate the respective buffered component and a biasing subcircuit configured to limit a magnitude of the respective component of the differential pulse-width modulation input signal driven to circuitry of the buffering subcircuit for driving the respective buffered component.
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公开(公告)号：US20220247367A1
公开(公告)日：2022-08-04
申请号：US17589047
申请日：2022-01-31
Inventor： John L. Melanson , Cory J. Peterson , Chandra Prakash , Ramin Zanbaghi , Eric Kimball
Abstract: Class-D amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include a first H-bridge driver circuit and a second H-bridge driver circuit. The class-D amplifier circuits also include a control circuit having an input for receiving an input signal to be reproduced by the class-D amplifier circuit. The control circuit has outputs coupled to inputs of the first and second H-bridge drivers, and includes one or more modulators. The control circuit selects between actively operating a selected one of the driver circuits or both, according to the signal to be reproduced, while setting an unselected driver circuit to turn either a high-side switch or a low-side switch of the unselected one of the first driver circuit or the second driver circuit fully on for at least some cycles of the one or more modulators.
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公开(公告)号：US20220149864A1
公开(公告)日：2022-05-12
申请号：US17096582
申请日：2020-11-12
Inventor： Chandra Prakash , Bhupendra Manola , John L. Melanson
IPC: H03M3/00
Abstract: An integrated circuit having multiple switched-capacitor delta-sigma data converter circuits includes compensation for voltage reference error due to leakage current that causes reference voltage droop. The reference filter capacitor terminal voltage is maintained by periodic connection to the reference feedback capacitor(s) that are alternately connected to a voltage reference buffer, and the leakage into the reference feedback capacitor networks of disabled converter circuits causes reference voltage droop. The compensation is either determined from the number of converter circuits that are disabled, or from an error between the filter capacitor voltage and a separate voltage reference, and may be applied by adjusting a resistance selectively coupled between the voltage reference buffer output and the filter capacitor, feedback applied to the voltage reference buffer or its input source. Alternatively, or in combination, correction may be applied to the output of the active converters by digital adjustment of output values.
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