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公开(公告)号：US11755894B2
公开(公告)日：2023-09-12
申请号：US16838495
申请日：2020-04-02
Inventor： Gordon James Bates , Toru Ido
CPC classification number: G06N3/063 , G11C11/54 , G11C13/0069 , G11C2013/0078
Abstract: This application relates to methods and apparatus for computing, especially to circuitry for performing computing, at least partly, in the analogue domain. The circuitry (200) comprises a plurality of memory cells (201), each memory cell having first and second paths between an electrode (202) for receiving an input current and respective positive and negative electrodes (203) for outputting a differential-current output. Memristors (101) are located in the first and second paths. The memory cells are configured into sets (205) of memory cells, the memory cells of each said set being connected so as to provide a differential current set output that corresponds to a combination of the cell outputs of all of the memory cells of that set. For each set, at least some of the memory cells of that set are configured to receive a different input current to other memory cells of that set.
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公开(公告)号：US10348275B2
公开(公告)日：2019-07-09
申请号：US16039760
申请日：2018-07-19
Inventor： Dario San Martin Molina , Gordon James Bates
Abstract: There is disclosed configurable frequency-divider circuitry for generating a target signal of a frequency Fr/Di based on a reference signal of a frequency Fr, where Di is an integer divider ratio, the frequency-divider circuitry comprising: N divider stages organised into a ring, each stage configured to receive an input signal and generate an output signal, with the output signal of each successive stage in the ring being the input signal of the next stage in the ring, wherein: the ring of stages is controlled by the reference signal so that the output signals are governed by the reference signal; the target signal is one of the output signals or a signal derived therefrom; and at least one of the stages is a configurable stage, whose mode of operation is configurable based on a configuration signal to configure the value of Di.
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Patent Agency Ranking
公开(公告)号：US11783171B2
公开(公告)日：2023-10-10
申请号：US16554984
申请日：2019-08-29
Inventor： Toru Ido , David Paul Singleton , Gordon James Bates , John Anthony Breslin
Abstract: This application relates to computing circuitry (200, 500, 600) for analogue computing. A plurality of current generators (201) are each configured to generate a defined current (ID1, ID2, . . . IDj) based on a respective input data value (D1, D2, . . . Dj). A memory array (202), having at least one set (204) of programmable-resistance memory cells (203), is arranged to receive the defined currents from each of the current generators at a respective signal line (206). Each set (204) of programmable-resistance memory cells (203) includes a memory cell associated with each signal line that, in use, can be connected between the relevant signal line and a reference voltage so as to generate a voltage on the signal line. An adder module (207) is coupled to each of the signal lines to generate a voltage at an output node (210) based on the sum of the voltages on each of the signal lines.
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公开(公告)号：US10935439B2
公开(公告)日：2021-03-02
申请号：US16105484
申请日：2018-08-20
Inventor： John Paul Lesso , Gordon James Bates
Abstract: This application relates to methods and apparatus for temperature monitoring for integrated circuits, and in particular to temperature monitoring using a locked-loop circuits, e.g. FLLs, PLLs or DLLs. According to embodiments a locked-loop circuit (200, 600) includes a controlled signal timing module (201, 601), wherein the timing properties of an output signal (SOUT, SFB) are dependent on a value of a control signal and on temperature. A controller (201, 601) compares a feedback signal (SFB) output from the timing module to a reference signal (SREF) and generates a control signal (SC) to maintain a desired timing relationship. A temperature monitor (202) monitors temperature based on the value of the control signal. For FLLs and PLLs the signal timing module may be a controlled oscillator (201).
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公开(公告)号：US12200946B2
公开(公告)日：2025-01-14
申请号：US18323838
申请日：2023-05-25
Inventor： John Paul Lesso , Gordon James Bates
Abstract: There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.
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公开(公告)号：US11696452B2
公开(公告)日：2023-07-04
申请号：US17308695
申请日：2021-05-05
Inventor： John Paul Lesso , Gordon James Bates
CPC classification number: H10B61/10 , G06N3/02 , G11C11/165 , H10N50/10
Abstract: There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.
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公开(公告)号：US11513010B2
公开(公告)日：2022-11-29
申请号：US17149444
申请日：2021-01-14
Inventor： John Paul Lesso , Gordon James Bates
Abstract: This application relates to methods and apparatus for temperature monitoring for integrated circuits, and in particular to temperature monitoring using a locked-loop circuits, e.g. FLLs, PLLs or DLLs. According to embodiments a locked-loop circuit includes a controlled signal timing module, wherein the timing properties of an output signal (SOUT, SFB) are dependent on a value of a control signal and on temperature. A controller compares a feedback signal (SFB) output from the timing module to a reference signal (SREF) and generates a control signal (SC) to maintain a desired timing relationship. A temperature monitor monitors temperature based on the value of the control signal. For FLLs and PLLs the signal timing module may be a controlled oscillator.
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