公开(公告)号：US20240280630A1

公开(公告)日：2024-08-22

申请号：US18651462

申请日：2024-04-30

申请人： Cisco Technology, Inc.

发明人： Sanjay SUNDER ,  Alexander C. KURYLAK

IPC分类号： G01R31/28

CPC分类号： G01R31/2853 ,  G01R31/2856

摘要： Techniques for testing connectivity between a first integrated circuit (IC) and a second IC of an electronics package are described. An example technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode of the second IC to forward biased. A connectivity test between the first and second ICs is performed, when the photodiode is forward biased. Another technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode in the second IC to reverse biased. A first voltage is measured at an input of a transimpedance amplifier (TIA) in the first IC when the photodiode is reverse biased. The switch(es) are controlled to change the bias direction of the photodiode to forward biased. A second voltage is measured at the input of the TIA when the photodiode is forward biased.

公开(公告)号：US20210067105A1

公开(公告)日：2021-03-04

申请号：US16553950

申请日：2019-08-28

申请人： Cisco Technology, Inc.

发明人： Alexander C. KURYLAK ,  Kadaba LAKSHMIKUMAR

IPC分类号： H03F3/08 ,  H04B10/69

摘要： In one embodiment, stable and controlled circuit element biasing is provided in a circuit comprising a voltage source operable to output a first voltage, a reference voltage source operable to output a reference voltage, a circuit element biased, during operation, by the first voltage at a first end and by a second voltage at a second end, a voltage controller coupled to the second end of the circuit element, wherein the voltage controller is operable to adjust the second voltage based on a gain output, a gain controller operable to receive the reference voltage as a first input and the second voltage as a second input, wherein the gain controller is operable to generate, at an output of the gain controller, the gain output based on the second voltage and the reference voltage, and a feedback loop that extends from the output of the gain controller, through the voltage controller, and to the second input.

公开(公告)号：US20240019485A1

公开(公告)日：2024-01-18

申请号：US17813203

申请日：2022-07-18

申请人： Cisco Technology, Inc.

发明人： Sanjay SUNDER ,  Alexander C. KURYLAK

IPC分类号： G01R31/28

CPC分类号： G01R31/2853 ,  G01R31/2856

摘要： Techniques for testing connectivity between a first integrated circuit (IC) and a second IC of an electronics package are described. An example technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode of the second IC to forward biased. A connectivity test between the first and second ICs is performed, when the photodiode is forward biased. Another technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode in the second IC to reverse biased. A first voltage is measured at an input of a transimpedance amplifier (TIA) in the first IC when the photodiode is reverse biased. The switch(es) are controlled to change the bias direction of the photodiode to forward biased. A second voltage is measured at the input of the TIA when the photodiode is forward biased.

公开(公告)号：US20230100245A1

公开(公告)日：2023-03-30

申请号：US17448822

申请日：2021-09-24

申请人： Cisco Technology, Inc.

发明人： Sanjay SUNDER ,  Alexander C. KURYLAK ,  Kadaba LAKSHMIKUMAR

IPC分类号： H03F3/45 ,  H03G3/30

摘要： An integrated circuit includes a transimpedance amplifier and an injection circuit. The injection circuit generates a first electrical test signal and injects the first electrical test signal into the transimpedance amplifier. The first electrical test signal or an output of the transimpedance amplifier generated based on the first electrical test signal is used to determine whether the integrated circuit is faulty.

公开(公告)号：US20210313971A1

公开(公告)日：2021-10-07

申请号：US16841593

申请日：2020-04-06

申请人： Cisco Technology, Inc.

发明人： Alexander C. KURYLAK ,  Kadaba LAKSHMIKUMAR

IPC分类号： H03K3/287 ,  H03K3/288

摘要： A flip-flop is provided that includes an input latch, configured to receive a data signal and a complement and produce set and reset pulses based on a clock and a difference between the data signal and the complement; and an output latch, configured to store a data value in a first memory and a complement data value in a second memory based on the set and reset pulses and the clock. Various buffers configured to invert and amplify the set and reset pulses before provision to the output latch stages are optionally disposed between the input and output latches. The input latch includes two signal arms, two difference transistors (one gate controlled by the clock and the other by a clock complement) coupled oppositely to one another (by respective drains and sources) to the signal arms, and two regeneration inverters coupled oppositely to one another to the signal arms.