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公开(公告)号：US20160112016A1
公开(公告)日：2016-04-21
申请号：US14698974
申请日：2015-04-29
Applicant: Cisco Technology, Inc.
Inventor： Kadaba LAKSHMIKUMAR , Craig APPEL
CPC classification number: H03F3/08 , H03F1/0205 , H03F1/086 , H03F3/45076 , H03F3/45183 , H03F3/45659 , H03F2200/135 , H03F2200/75 , H03F2203/45026 , H03F2203/45082 , H03F2203/45088 , H03F2203/45116 , H03F2203/45208 , H03F2203/45221 , H03F2203/45336 , H03F2203/45402 , H03F2203/45418 , H03F2203/45434 , H03F2203/45436 , H03F2203/45481 , H03F2203/45594 , H03F2203/45604 , H03F2203/45642 , H03F2203/45648 , H03F2203/45664
Abstract: Embodiments generally relate to a conversion arrangement, a driver arrangement, and a method of producing a complementary complementary metal-oxide-semiconductor (CMOS) output signal for driving a modulator device. The conversion arrangement includes a differential amplifier configured to produce a first amplified signal based on the differential input signal, and at least two transimpedance amplifiers (TIAs) coupled with respective outputs of the differential amplifier and configured to produce a second amplified signal based on the first amplified signal. Respective bias voltages for the TIAs are based on the first amplified signal. The conversion arrangement further includes a common-mode feedback arrangement coupled with outputs of the TIAs and configured to control the first amplified signal based on the second amplified signal, thereby controlling the bias voltages, wherein the complementary CMOS output signal is based on the second amplified signal.
Abstract translation: 实施例通常涉及转换装置，驱动器装置和产生用于驱动调制器装置的互补金属氧化物半导体（CMOS）输出信号的方法。 转换装置包括：差分放大器，被配置为基于差分输入信号产生第一放大信号，以及至少两个跨阻抗放大器（TIAs），其耦合到差分放大器的相应输出端，并被配置为基于第一信号产生第二放大信号 放大信号。 TIA的相应偏置电压基于第一个放大信号。 转换装置还包括与TIA的输出耦合并配置为基于第二放大信号控制第一放大信号的共模反馈装置，从而控制偏置电压，其中互补CMOS输出信号基于第二放大 信号。
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公开(公告)号：US20210067105A1
公开(公告)日：2021-03-04
申请号：US16553950
申请日：2019-08-28
Applicant: Cisco Technology, Inc.
Inventor： Alexander C. KURYLAK , Kadaba LAKSHMIKUMAR
Abstract: In one embodiment, stable and controlled circuit element biasing is provided in a circuit comprising a voltage source operable to output a first voltage, a reference voltage source operable to output a reference voltage, a circuit element biased, during operation, by the first voltage at a first end and by a second voltage at a second end, a voltage controller coupled to the second end of the circuit element, wherein the voltage controller is operable to adjust the second voltage based on a gain output, a gain controller operable to receive the reference voltage as a first input and the second voltage as a second input, wherein the gain controller is operable to generate, at an output of the gain controller, the gain output based on the second voltage and the reference voltage, and a feedback loop that extends from the output of the gain controller, through the voltage controller, and to the second input.
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Patent Agency Ranking
公开(公告)号：US20230100245A1
公开(公告)日：2023-03-30
申请号：US17448822
申请日：2021-09-24
Applicant: Cisco Technology, Inc.
Inventor： Sanjay SUNDER , Alexander C. KURYLAK , Kadaba LAKSHMIKUMAR
Abstract: An integrated circuit includes a transimpedance amplifier and an injection circuit. The injection circuit generates a first electrical test signal and injects the first electrical test signal into the transimpedance amplifier. The first electrical test signal or an output of the transimpedance amplifier generated based on the first electrical test signal is used to determine whether the integrated circuit is faulty.
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公开(公告)号：US20210313971A1
公开(公告)日：2021-10-07
申请号：US16841593
申请日：2020-04-06
Applicant: Cisco Technology, Inc.
Inventor： Alexander C. KURYLAK , Kadaba LAKSHMIKUMAR
Abstract: A flip-flop is provided that includes an input latch, configured to receive a data signal and a complement and produce set and reset pulses based on a clock and a difference between the data signal and the complement; and an output latch, configured to store a data value in a first memory and a complement data value in a second memory based on the set and reset pulses and the clock. Various buffers configured to invert and amplify the set and reset pulses before provision to the output latch stages are optionally disposed between the input and output latches. The input latch includes two signal arms, two difference transistors (one gate controlled by the clock and the other by a clock complement) coupled oppositely to one another (by respective drains and sources) to the signal arms, and two regeneration inverters coupled oppositely to one another to the signal arms.
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公开(公告)号：US20220345102A1
公开(公告)日：2022-10-27
申请号：US17302001
申请日：2021-04-21
Applicant: Cisco Technology, Inc.
Inventor： Abhishek BHAT , Romesh Kumar NANDWANA , Kadaba LAKSHMIKUMAR
Abstract: A multi-port coupled inductor with interference suppression is provided with a first signal port connected to a first resistor port via a first inductor; a second resistor port connected to the first resistor port via a second inductor; a second signal port connected to the second resistor port via a third inductor; a third resistor port connected to the first resistor port via a first resistor; a fourth resistor port connected to the third resistor port via a fourth inductor and to the second resistor port via a second resistor; a third signal port connected to the third resistor port via a fifth inductor; and a fourth signal port connected to the fourth resistor port via a sixth inductor.
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公开(公告)号：US20220182064A1
公开(公告)日：2022-06-09
申请号：US17115570
申请日：2020-12-08
Applicant: Cisco Technology, Inc.
Inventor： Yongxin LI , Romesh Kumar NANDWANA , Kadaba LAKSHMIKUMAR
Abstract: An apparatus includes a first digital-to-time converter (DTC) and a second DTC. The first DTC includes a sequence of delay stages. Each of the delay stages adds a delay to an input signal based on a control signal. Each delay stage includes a comparator and a capacitor coupled to an input of the comparator and to ground. The second DTC is coupled in parallel to the first DTC. The second DTC adds a delay to the input signal based on a complement of the control signal.
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公开(公告)号：US20170244416A1
公开(公告)日：2017-08-24
申请号：US15048040
申请日：2016-02-19
Applicant: Cisco Technology, Inc.
Inventor： Kadaba LAKSHMIKUMAR , Mark Y. TSE , Bibhu DAS , Bipin DAMA
CPC classification number: H03L7/0807 , H03L7/087 , H03L7/093 , H03L7/095 , H03L7/113 , H04L7/0004 , H04L7/033 , H04L7/0331
Abstract: Embodiments herein describe a reference-less CDR circuit that receives electrical signals that may have been transmitted along either an electrical or optical interconnect which are then processed to identify the original data. To do so, the CDR circuit includes a frequency locking loop (FLL) and a phase locking loop (PLL) which generate control signals for a voltage controlled oscillator (VCO). In one embodiment, the FLL generates a coarse adjustment signal which the VCO uses to output a recovered clock that substantially matches the frequency of the received electrical signal. The PLL, on the other hand, generates a fine adjustment signal which the VCO uses to make small adjustments (e.g., half cycle phase shifts) to the recovered clock. The recovered clock outputted by the VCO is then fed back and used as an input in both the FLL and the PLL.
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