公开(公告)号：US09673910B1

公开(公告)日：2017-06-06

申请号：US14629243

申请日：2015-02-23

Applicant: ClariPhy Communications, Inc.

Inventor： Diego Ernesto Crivelli ,  Mario Rafael Hueda ,  Hugo Santiago Carrer ,  Jeffrey Zachan ,  Vadim Gutnik ,  Martin Ignacio del Barco ,  Shih Cheng Wang ,  Geoffrey O. Hatcher ,  Jorge Manuel Finochietto ,  Michael Yeo ,  Andre Chartrand ,  Norman L. Swenson ,  Paul Voois ,  Oscar Ernesto Agazzi ,  Ramiro Rogelio Lopez

IPC: H04B10/00 ,  H04B10/61 ,  H04B10/40 ,  H04B10/2569 ,  H04J14/00

CPC classification number: H04B10/6162 ,  H04B10/2569 ,  H04B10/40 ,  H04B10/6161

Abstract: A transceiver for fiber optic communications.

公开(公告)号：US09071364B1

公开(公告)日：2015-06-30

申请号：US13655302

申请日：2012-10-18

Applicant: ClariPhy Communications, Inc.

Inventor： Paul Voois ,  Diego Ernesto Crivelli ,  Ramiro Rogelio Lopez ,  Jorge Manuel Finochietto ,  Oscar Ernesto Agazzi

IPC: H04B10/04 ,  H04B10/00 ,  H04B10/12 ,  H04B10/58 ,  H04B10/2507 ,  H04B10/40

CPC classification number: H04B10/40 ,  H04B10/2507 ,  H04B10/58

Abstract: An optical communication system provides coherent optical transmission for metro applications. Relative to conventional solutions, the optical communication system can be implemented with reduced cost and can operate with reduced power consumption, while maintaining high data rate performance (e.g., 100 G). Furthermore, a programmable transceiver enables compatibility with a range of different types of optical networks having varying performance and power tradeoffs. In one embodiment, the optical communication system uses 100 Gb/s dual-polarization 16-point quadrature amplitude modulation (DP-16QAM) with non-linear pre-compensation of Indium Phosphide (InP) optics for low power consumption.

Abstract translation: 光通信系统为城域应用提供相干光传输。 相对于传统解决方案，光通信系统可以以降低的成本实现，并且可以在降低功耗的情况下工作，同时保持高数据速率性能（例如，100G）。 此外，可编程收发器能够与具有不同性能和功率权衡的不同类型的光网络兼容。 在一个实施例中，光通信系统使用具有用于低功耗的铟磷化物（InP）光学器件的非线性预补偿的100Gb / s双极化16点正交幅度调制（DP-16QAM）。

公开(公告)号：US09571308B1

公开(公告)日：2017-02-14

申请号：US14581934

申请日：2014-12-23

Applicant: ClariPhy Communications, Inc.

Inventor： Marcel Louis Lugthart ,  Jeffrey Zachan ,  Linghsiao Jerry Wang ,  Paul Voois ,  Neel H. Patel ,  Norman L. Swenson ,  Scott Powell

IPC: H04L27/18 ,  H04L25/03 ,  H04L27/38 ,  H04L5/14 ,  H04B1/40

CPC classification number: H04L7/0037 ,  H03M5/12 ,  H04B1/40 ,  H04L5/14 ,  H04L7/0016 ,  H04L7/0054 ,  H04L7/0062 ,  H04L7/0087 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L25/03006 ,  H04L25/14 ,  H04L27/02 ,  H04L27/38 ,  H04L47/70

Abstract: Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.

Abstract translation: 这里描述了用于高速通信的系统和方法。 在某些方面，系统和方法包括用于重新定时，多路复用，解复用和传输数据的创新收发器架构和技术。 系统和方法可用于实现不同电子设备，计算设备，存储设备和外围设备之间可靠的高速点对点通信。

公开(公告)号：US09337934B1

公开(公告)日：2016-05-10

申请号：US14093306

申请日：2013-11-29

Applicant: ClariPhy Communications, Inc.

Inventor： Oscar Ernesto Agazzi ,  Diego Ernesto Crivelli ,  Paul Voois ,  Ramiro Rogelio Lopez ,  Jorge Manuel Finochietto ,  Norman L. Swenson ,  Mario Rafael Hueda ,  Hugo Santiago Carrer ,  Vadim Gutnik ,  Ulises Morales ,  Martin Ignacio del Barco ,  Martin Carlos Asinari ,  Federico Nicolas Paredes ,  Alfredo Javier Taddei ,  Mauro M. Bruni ,  Damian Alfonso Morero ,  Facundo Abel Alcides Ramos ,  Laura Maria Ferster ,  Elvio Adrian Serrano ,  Pablo Gustavo Quiroga ,  Roman Antonio Arenas ,  Matias German Schnidrig ,  Alejandro Javier Schwoykoski

IPC: H04B10/00 ,  H04B10/40

CPC classification number: H04B10/516 ,  H04B10/40 ,  H04B10/61 ,  H04L7/0075

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract translation: 相干接收机包括具有入口线路侧接口和入口主机侧接口的入口信号路径。 入口信号路径被配置为在入口侧接口处接收模拟信号向量，以解调模拟信号向量，并在入口主机侧接口输出数字数据信号。 相干接收机还包括被配置为接收单个参考时钟信号并且向入口信号路径的不同分量提供多个经修改的入口路径时钟信号的时钟和定时电路，所述多个修改的入口路径时钟信号从单个参考 时钟信号和具有不同时钟速率的多个修改的入口路径时钟信号。 接收器，发射器或收发器可以以多种可编程操作模式操作，以适应不同的调制/解调方案，纠错码方案，成帧/映射协议或其他可编程特征。

公开(公告)号：US09136942B2

公开(公告)日：2015-09-15

申请号：US13952774

申请日：2013-07-29

Applicant: ClariPhy Communications, Inc.

Inventor： Thomas A. Lindsay ,  Norman L. Swenson ,  Paul Voois

IPC: H04B10/073 ,  H04B10/66 ,  H04B17/00 ,  H04B17/345

CPC classification number: H04B10/073 ,  H04B10/66 ,  H04B17/345

Abstract: A receiver for a communications link includes a receiver module and a host receiver. These two components can be tested independently. In one embodiment, the receiver module is characterized with respect to noise and distortion. The noise performance can be determined by comparing input and output signals of the receiver module, to determine the relative noise of the receiver module. The distortion performance can be determined by comparing the distortion of input and output signals of the receiver module, using a reference host receiver that includes an equalizer. The host receiver can be tested by using a reference receiver module.

Abstract translation: 用于通信链路的接收机包括接收机模块和主机接收机。 这两个组件可以独立测试。 在一个实施例中，接收器模块的特征在于噪声和失真。 可以通过比较接收机模块的输入和输出信号来确定噪声性能，以确定接收机模块的相对噪声。 可以通过使用包括均衡器的参考主机接收机比较接收机模块的输入和输出信号的失真来确定失真性能。 主机接收机可以通过使用参考接收机模块进行测试。

公开(公告)号：US20140161440A1

公开(公告)日：2014-06-12

申请号：US13952774

申请日：2013-07-29

Applicant: ClariPhy Communications, Inc.

Inventor： Thomas A. Lindsay ,  Norman L. Swenson ,  Paul Voois

IPC: H04B10/073

CPC classification number: H04B10/073 ,  H04B10/66 ,  H04B17/345

Abstract: A receiver for a communications link includes a receiver module and a host receiver. These two components can be tested independently. In one embodiment, the receiver module is characterized with respect to noise and distortion. The noise performance can be determined by comparing input and output signals of the receiver module, to determine the relative noise of the receiver module. The distortion performance can be determined by comparing the distortion of input and output signals of the receiver module, using a reference host receiver that includes an equalizer. The host receiver can be tested by using a reference receiver module.

Abstract translation: 用于通信链路的接收机包括接收机模块和主机接收机。 这两个组件可以独立测试。 在一个实施例中，接收器模块的特征在于噪声和失真。 可以通过比较接收机模块的输入和输出信号来确定噪声性能，以确定接收机模块的相对噪声。 可以通过使用包括均衡器的参考主机接收机比较接收机模块的输入和输出信号的失真来确定失真性能。 主机接收机可以通过使用参考接收机模块进行测试。