公开(公告)号：US06192441B1

公开(公告)日：2001-02-20

申请号：US08690926

申请日：1996-08-01

申请人： Claude Athenes ,  Pascal Moniot

发明人： Claude Athenes ,  Pascal Moniot

IPC分类号： G06F700

CPC分类号： G06F13/24

摘要： This device controls the interrupts of a microprocessor based on events occurring in at least one entity associated with this microprocessor. The device organizes the storage of words representative of at least an origin and a type of the interrupt issued by the entity. The interrupts from the entity are stored in an area of a memory. When there is more than one entity, each entity has an area of memory allocated to it. The microprocessor can access these memory areas and process the interrupts. An indicator is also provided so that the device can tell when a memory area has become full.

摘要翻译： 该设备基于与该微处理器相关联的至少一个实体中发生的事件来控制微处理器的中断。 该装置组织代表由该实体发出的至少一个起始点和一个中断类型的字的存储。 来自实体的中断存储在存储器的区域中。 当有多个实体时，每个实体都有一个内存分配区域。 微处理器可以访问这些存储区域并处理中断。 还提供了一个指示符，使得该设备可以告诉存储区何时已满。

公开(公告)号：US4317008A

公开(公告)日：1982-02-23

申请号：US143555

申请日：1980-04-25

申请人： Claude Athenes ,  Jean L. J. Meresse ,  Jacques E. Salle

发明人： Claude Athenes ,  Jean L. J. Meresse ,  Jacques E. Salle

IPC分类号： H04Q11/04 ,  H04Q3/60

CPC分类号： H04Q11/04

摘要： The modular switching network for time-division telephone exchanges, which may be applied to small-capacity time-division telephone exchanges, is constituted by the direct connection of pairs of subscriber and trunk line connecting units by PCM digital trunks, each connecting unit comprising a concentration-deconcentrator device for serving the subscribers associated with this connecting unit.

摘要翻译： 可应用于小容量时分电话交换机的时分电话交换的模块化交换网络由PCM数字中继线直接连接用户和中继线连接单元，每个连接单元包括 集中分配器装置，用于服务与该连接单元相关联的用户。

公开(公告)号：US4095048A

公开(公告)日：1978-06-13

申请号：US696197

申请日：1976-06-15

申请人： Claude Athenes ,  Jean Pierre Landez

发明人： Claude Athenes ,  Jean Pierre Landez

IPC分类号： H04J3/06 ,  H04L25/05 ,  H04Q11/04 ,  H04L7/00

CPC分类号： H04L25/05 ,  H04J3/0626 ,  H04Q11/04

摘要： The invention provides a method of synchronization of a junction in a pulse-code modulation (PCM) transmission network where any two multiplexing-demultiplexing stations equipped with independents clocks have to be brought into synchronism. For this purpose, the pulse trains (T.I.) of the PCM junction are alternatively recorded on two parallel channels A and B (registers RPA and RPB) and then memorized in a frame memory (MTR) by repeating the reading of the register when a risk of error is detected by comparison of the clocks. Means are provided for relocating the T.I. containing the multiframe locking code and the first frame of multiframe.

公开(公告)号：US4074077A

公开(公告)日：1978-02-14

申请号：US684964

申请日：1976-05-10

申请人： Pierre Charransol ,  Jacques Hauri ,  Claude Athenes

发明人： Pierre Charransol ,  Jacques Hauri ,  Claude Athenes

IPC分类号： H04Q11/04 ,  H04J3/00

CPC分类号： H04Q11/04

摘要： The invention relates to time-division exchanges in which the connection between the subscribers is established successively in time at the same frequency as a sampling of telephone signals. It consists in carrying out the spatial multiplex switching stage simultaneously on k words in series mode, each word using a separate spatial multiplex switch. A spatial multiplex switching stage with k independent elements is thus provided.This invention relates to time-division exchanges, in which the connection between the subscribers is established successively in time at the same rate as a sampling of telephone signals. The invention also relates to methods reshaping an exchange of this kind.These signals are generally sampled at a frequency of 8kc/s, after which the value of each sample is coded by a number of 8 bits. In most cases, this is followed by concentration which makes it possible, for example, to reduce the number of subscribers capable of being simultaneously connected from 256 to 32, the others awaiting a free connection. The degree of concentration is governed by the traffic expected on the subscriber lines which is known statistically. In general, the concentration circuit then delivers a frame of 32 channels multiplexed in time which is supported by a so-called multiplex junction circuit. It is also possible to carry out concentration with analogue samples, followed by encoding.The above mentioned numerical values are not critical, although they are generally used because of national and international standards.One significant problem is to guarantee adequate safety of operations in the event of failure of an element so that, instead of all the lines served by the automatic switching system having to be taken out of service, the blocking level is merely increased to a small extent.One solution to this problem is described in French Patent Application No. 75.05799. It comprises dividing shaping of an exchange of the type in question into n identical and independent sections connected at the level of the space-division switches by n busbars. Considering these spatial multiplex switches thus connected as a whole, it is apparent that they could be placed in the form of a matrix with n inputs and n outputs comprising n.sup.2 connection points.In the case of a high-capacity exchange this number of connection points would be too high. One known solution to this problem comprises using a multistage spatial multiplex switching network made up of a large number of matrices of small dimensions. Finally the number of connection points of these matrices as a whole is distinctly below n.sup.2, but it is no longer possible to return to the structure described above and the preceding protection system is no longer applicable.However, protection is essential, especially at the level of the spatial multiplex switch, because switching matrices are integrated in one and the same housing in which the failure of one element has consequential effects on all the others. Taking as an example a very simple integrated circuit comprising 4 multiplexers with 8 multiple inputs and used in the normal way in a connection network operating in parallel mode at a frequency of 2 MHz, this circuit will be used for more than 1000 calls. A failure of a circuit such as this is extremely serious.Various processes for replacing all or some of the safety elements of the switching network have already been proposed. These processes are attended by the disadvantage of requiring a large number of switches which, even if they are of the static type, may themselves be the origin of failures. In addition, the rescue switching procedure is complex and involves the loss of a large number of calls.In accordance with the present invention a time-division exchange is provided for switching binary words of k bits from a plurality of incoming parallel-mode PCM junctions to a plurality of output parallel-mode PCM junctions, said exchange comprising:first time-division switching means connected to said incoming PCM junctions for delivering said binary words in parallel mode;parallel-series conversion means for receiving said binary words from said first time-division switching means and delivering said binary words in series mode on k + n pluralities of input connections;matrix switching means connected to said k + n pluralities of input connections for delivering said binary words in series mode on k + n pluralities of output connections; said matrix switching means being divided into k + n independent distinct elements, each of said elements being connected respectively to one of said pluralities of input connections and to one of said pluralities of output connections and presenting to said binary words a plurality of paths between said input connections and said output connections;series-parallel conversion means connected to said k + n pluralities of output connections for delivering said binary words in parallel mode; andsecond time-division switching means connected to said series parallel conversion means for delivering said binary words to said plurality of output parallel-mode PCM junctions.

摘要翻译： 本发明涉及时分交换，其中用户之间的连接在时间上以与电话信号的采样相同的频率连续建立。 它包括在串行模式下在k个字上同时执行空间复用切换级，每个单词使用单独的空间复用开关。 因此提供了具有k个独立元件的空间多路复用切换级。

公开(公告)号：US06584523B1

公开(公告)日：2003-06-24

申请号：US09478600

申请日：2000-01-06

申请人： Claude Athenes ,  Bernard Louis-Gavet

发明人： Claude Athenes ,  Bernard Louis-Gavet

IPC分类号： G06F1300

CPC分类号： G06F13/18

摘要： This invention relates to a device for organizing access to a bus connecting a memory to at least two entities asynchronous binary signals representing requests for access to the bus. The device supplies binary signals to authorize the access to an entity based on a priority determination between the different requests and includes a priority decoder in wired logic associated with an input register. A loading of the state of the access request signals happens, if an access request is present while a read or write cycle of the memory is executed, upon the arrival of a pulse on a signal issued by a memory controller associated with the memory and indicative of the end of a memory cycle.

摘要翻译： 本发明涉及一种用于组织对总线的访问的设备，该总线将存储器连接到表示对总线访问的请求的至少两个实体的异步二进制信号。 该设备提供二进制信号以根据不同请求之间的优先级确定授权对实体的访问，并且包括与输入寄存器相关联的有线逻辑中的优先级解码器。 当存储器的读或写周期执行时存在访问请求信号的状态的加载，当脉冲到由存储器关联的存储器控​​制器发出的信号和指示 的记忆周期结束。

公开(公告)号：US5878279A

公开(公告)日：1999-03-02

申请号：US690928

申请日：1996-08-01

申请人： Claude Athenes

发明人： Claude Athenes

IPC分类号： G06F13/30 ,  H04L29/06 ,  G06F13/26

CPC分类号： H04L29/06 ,  G06F13/30

摘要： This invention relates to an integrated HDLC circuit of the type including at least one HDLC controller and one DMA controller, and means for organizing the access to a first external bus for connection to an external memory, via an internal bus to which are connected different entities, which require to have access to the external memory, the internal bus being connected to the first external bus via a memory controller integrated in the HDLC circuit.

摘要翻译： 本发明涉及一种包括至少一个HDLC控制器和一个DMA控制器的集成HDLC电路，以及用于经由连接到不同实体的内部总线来组织对第一外部总线的访问以连接到外部存储器的装置 ，其需要访问外部存储器，内部总线通过集成在HDLC电路中的存储器控​​制器连接到第一外部总线。

公开(公告)号：US4644382A

公开(公告)日：1987-02-17

申请号：US820895

申请日：1986-01-17

申请人： Pierre Charransol ,  Jean C. Audrix ,  Claude Athenes

发明人： Pierre Charransol ,  Jean C. Audrix ,  Claude Athenes

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L27/118 ,  H01L29/78

CPC分类号： H01L27/11807 ,  H01L27/092

摘要： A prediffused integrated circuit having rows of basic cells on a substrate. Each basic cell includes two MOS transistors connected in series through a common drain or source electrode, each transistor having a separate gate. All basic cells in a row are the same type while adjacent rows alternate between p-type and n-type.

摘要翻译： 一种在基板上具有基本单元行的预扩充集成电路。 每个基本单元包括通过公共漏极或源极串联连接的两个MOS晶体管，每个晶体管具有单独的栅极。 一行中的所有基本单元格都是相同的类型，而相邻的行在p型和n型之间交替。

公开(公告)号：US5083291A

公开(公告)日：1992-01-21

申请号：US351224

申请日：1989-05-15

申请人： Claude Athenes ,  Jean-Louis Bernet ,  Jean-Bernard Saxod

发明人： Claude Athenes ,  Jean-Louis Bernet ,  Jean-Bernard Saxod

IPC分类号： H04J3/06

CPC分类号： H04J3/0626

摘要： A process for converting a first flow of data words supplied at the rate of a first clock into a second flow of data words comprising, inside the successive frames, a sequence of n data words of the first flow and accompanying data, the duration of each frame of the second flow being equal to the duration of n data words in the first flow. Said process comprises: storing the successive data words of the first flow in an input register (1); as soon as the register is full, writing its content in one of p intermediate registers (A, B, C); sequentially reading the p intermediate registers in an output register (5); and if, during a frame, the writing and reading sequence in the intermediate registers is such that an intermediate register is read while its writing has not been modified, skipping, at the beginning of the following frame, one reading order until one obtains an adequate synchronization which will then be maintained during the subsequent frames.

摘要翻译： 用于将以第一时钟的速率提供的数据字的第一流转换成第二数据字流的过程，该数据字在连续帧内包括第一流和其伴随数据的n个数据字的序列，每个持续时间 第二流的帧等于第一流中的n个数据字的持续时间。 所述处理包括：将第一流的连续数据字存储在输入寄存器（1）中; 一旦寄存器满了，将其内容写入p个中间寄存器（A，B，C）之一; 顺序读取输出寄存器（5）中的p个中间寄存器; 并且如果在帧期间中间寄存器中的写入和读取顺序使得在其写入尚未被修改的同时读取中间寄存器，则在随后的帧的开始处跳过一个读取顺序直到获得足够的 然后在随后的帧期间将其保持同步。

公开(公告)号：US4491837A

公开(公告)日：1985-01-01

申请号：US361812

申请日：1982-03-23

申请人： Claude Athenes ,  Francois Tarbouriech ,  Gerard Poux

发明人： Claude Athenes ,  Francois Tarbouriech ,  Gerard Poux

IPC分类号： H04Q11/04

CPC分类号： H04Q11/0407

摘要： A logic selection module for forming the interface between the two central units and eight selection circuits of an electronic time automatic telephone switchboard and which comprises means for selecting the calling central unit, means for connecting the thus selected central unit, means for decoding the address of one of the eight selection circuits to which the module is connected in the signal received from the thus selected central unit and means for transmitting the marking signals received from the central unit to the said circuit, whose address has been decoded.

摘要翻译： 一种用于形成电子时间自动电话交换机的两个中央单元和八个选择电路之间的接口的逻辑选择模块，其包括用于选择呼叫中心单元的装置，用于连接这样选择的中央单元的装置， 在从所选择的中央单元接收的信号中连接模块的八个选择电路中的一个和用于将从中央单元接收的标记信号发送到已经被解码地址的所述电路的装置。

公开(公告)号：US4224475A

公开(公告)日：1980-09-23

申请号：US4237

申请日：1979-01-17

申请人： Pierre Charransol ,  Claude Athenes ,  Jacques Salle

发明人： Pierre Charransol ,  Claude Athenes ,  Jacques Salle

IPC分类号： H04Q3/52 ,  H04Q11/04

CPC分类号： H04Q11/04

摘要： A switching system for telephone exchanges employing pulse code modulation (PCM). The time division switching network uses standard circuits of a single type, i.e., symmetrical time division matrices (MTS) and, in a particular embodiment, one PCM telephone junction is multipled onto two inputs of two MTSs and the latter are rejoined by two bi-directional junctions so that the construction of telephone exchange according to the invention permits simple and easy extensions of the capacity of the switching system.

摘要翻译： 一种采用脉码调制（PCM）的电话交换系统。 时分交换网络使用单一类型的标准电路，即对称时分矩阵（MTS），并且在特定实施例中，一个PCM电话连接被乘以两个MTS的两个输入，并且后者由两个双向 定向接点，使得根据本发明的电话交换机的构造允许简单和容易地扩展交换系统的容量。