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    Apparatus for postponing processing of interrupts by a microprocessor
    1.
    发明授权
    Apparatus for postponing processing of interrupts by a microprocessor 失效
    用于延迟由微处理器处理中断的装置

    公开(公告)号：US06192441B1

    公开(公告)日：2001-02-20

    申请号：US08690926

    申请日：1996-08-01

    申请人： Claude Athenes ,  Pascal Moniot

    发明人： Claude Athenes ,  Pascal Moniot

    IPC分类号： G06F700

    CPC分类号： G06F13/24

    摘要： This device controls the interrupts of a microprocessor based on events occurring in at least one entity associated with this microprocessor. The device organizes the storage of words representative of at least an origin and a type of the interrupt issued by the entity. The interrupts from the entity are stored in an area of a memory. When there is more than one entity, each entity has an area of memory allocated to it. The microprocessor can access these memory areas and process the interrupts. An indicator is also provided so that the device can tell when a memory area has become full.

    摘要翻译： 该设备基于与该微处理器相关联的至少一个实体中发生的事件来控制微处理器的中断。 该装置组织代表由该实体发出的至少一个起始点和一个中断类型的字的存储。 来自实体的中断存储在存储器的区域中。 当有多个实体时，每个实体都有一个内存分配区域。 微处理器可以访问这些存储区域并处理中断。 还提供了一个指示符，使得该设备可以告诉存储区何时已满。

    Method for associating a first address with a second address of reduced size for directly addressing a context memory on a computer
    4.
    发明授权
    Method for associating a first address with a second address of reduced size for directly addressing a context memory on a computer 有权
    用于将第一地址与缩小尺寸的第二地址相关联以便直接寻址计算机上的上下文存储器的方法

    公开(公告)号：US07275077B2

    公开(公告)日：2007-09-25

    申请号：US10395041

    申请日：2003-03-21

    申请人： Pascal Moniot ,  David Furodet

    发明人： Pascal Moniot ,  David Furodet

    IPC分类号： G06F15/16 ,  G06F9/26 ,  H04L12/28

    CPC分类号： H04L61/6022 ,  H04L29/12009 ,  H04L29/12801 ,  H04L29/12839 ,  H04L61/6004

    摘要： A method for associating with a first address a second address of reduced size, comprising: calculating a first intermediary address by the first address, the first intermediary address having a reduced size with respect to the first address; then choosing as a second address the first intermediary address if this second address is not associated with another first address, or, otherwise, calculating a second intermediary address by a first polynomial division of the first address, the second intermediary address having a reduced size as compared to the first address; then choosing as a second address the second intermediary address.

    摘要翻译： 一种用于将缩小尺寸的第二地址与第一地址相关联的方法，包括：通过所述第一地址计算第一中间地址，所述第一中间地址相对于所述第一地址具有减小的大小; 然后如果该第二地址不与另一个第一地址相关联，则选择第二地址作为第二中间地址，否则，通过第一地址的第一多项式除法来计算第二中间地址，第二中间地址的大小减小为 与第一个地址相比; 然后选择第二个地址作为第二个中间地址。

    Method and circuit for providing a context datum of a device based on an address associated with this device
    7.
    发明授权
    Method and circuit for providing a context datum of a device based on an address associated with this device 有权
    用于基于与该设备相关联的地址来提供设备的上下文数据的方法和电路

    公开(公告)号：US07424022B2

    公开(公告)日：2008-09-09

    申请号：US10394506

    申请日：2003-03-21

    申请人： Pascal Moniot ,  David Furodet

    发明人： Pascal Moniot ,  David Furodet

    IPC分类号： H04L12/28 ,  G06F12/00

    CPC分类号： H04L12/56 ,  H04L45/742

    摘要： A method for providing a context datum associated with a source and/or destination device based on an address datum associated with the device, including addressing, based on the address datum, a unit for providing an index, the unit containing, for each address datum, an indicator indicating whether the device is active; and addressing, based on the index provided by the unit, a context memory for providing the context datum associated with the device.

    摘要翻译： 一种用于基于与所述设备相关联的地址数据提供与源和/或目的地设备相关联的上下文数据的方法，包括基于所述地址数据寻址用于提供索引的单元，所述单元包含针对每个地址基准 指示设备是否活动的指示灯; 以及基于由所述单元提供的索引来寻址用于提供与所述设备相关联的上下文数据的上下文存储器。

    System for controlling the rates of concurrent transmissions on a communication channel
    8.
    发明授权
    System for controlling the rates of concurrent transmissions on a communication channel 有权
    用于控制通信信道上并发传输速率的系统

    公开(公告)号：US06876662B1

    公开(公告)日：2005-04-05

    申请号：US09491789

    申请日：2000-01-26

    申请人： Pascal Moniot

    发明人： Pascal Moniot

    IPC分类号： H04L13/08 ,  H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  H04L12/26 ,  G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J3/14

    CPC分类号： H04L12/5602 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04Q11/0478

    摘要： A method is provided for controlling the rates of concurrent digital transmissions using at least a first queue having a plurality of locations. For each transmission, an index corresponding to a data cell of the transmission is written at one of the locations in the first queue, and the locations of the first queue are successively surveyed at a rate corresponding to a cell transmission rate. If the surveyed location in the first queue contains an index, the corresponding data cell is transmitted, the location is freed, and the index is rewritten at the location in the first queue that is distant from the surveyed location by a value determined by the rate of the corresponding transmission. In one preferred method, indexes corresponding to high priority transmissions are written into the first queue and indexes corresponding to lower priority transmissions are written into a second queue. Also provided is a method for controlling the rates of concurrent digital transmissions using at least first and second queues.

    摘要翻译： 提供了一种用于使用至少具有多个位置的第一队列来控制并行数字传输速率的方法。 对于每个传输，对应于传输的数据单元的索引被写入第一队列中的一个位置，并且以对应于小区传输速率的速率连续地测量第一队列的位置。 如果第一队列中的受访位置包含索引，则发送对应的数据单元，释放位置，并且在远离测量位置的第一队列中的位置重写索引，该值由该速率确定 的相应传输。 在一个优选方法中，对应于高优先级传输的索引被写入第一队列，并且对应于较低优先级传输的索引被写入第二队列。 还提供了一种用于使用至少第一和第二队列来控制并行数字传输速率的方法。

    Device for associating indexes to addresses chosen from a greater number than the number of available indexes
    9.
    发明授权
    Device for associating indexes to addresses chosen from a greater number than the number of available indexes 有权
    用于将索引关联到从比可用索引数量更大的数字中选择的地址的设备

    公开(公告)号：US06850527B1

    公开(公告)日：2005-02-01

    申请号：US09523572

    申请日：2000-03-10

    申请人： Pascal Moniot

    发明人： Pascal Moniot

    IPC分类号： G06F17/30 ,  H04L12/70 ,  H04L12/935 ,  H04Q11/04 ,  H04L12/28 ,  H04J3/07

    CPC分类号： H04L49/309 ,  H04L49/3009 ,  H04L2012/5618 ,  H04Q11/0478

    摘要： A device for associating indexes to addresses chosen from among a greater number of values than the number of available indexes, including a memory containing indexes and respective check words corresponding to predetermined bits of the addresses associated with the indexes; a packing circuit receiving a current address and suppressing in this address bits determined by a pattern such that the suppressed bits correspond to bits of the check words, the packed address provided by the packing circuit being used to select in the read mode a memory location; and a comparator indicating that the current address corresponds to the selected memory location if the bits of the check word of the selected location are equal to the corresponding bits of the current address.

    摘要翻译： 一种用于将索引与从可用索引数量比较多的值中选择的地址相关联的设备，包括包含与索引相关联的地址的预定比特对应的索引和相应检查字的存储器; 接收当前地址并且抑制由地址确定的地址比特的打包电路，使得被禁止的比特与校验字的比特相对应，由打包电路提供的打包地址用于在读取模式中选择一个存储位置; 以及指示当前地址对应于所选择的存储器位置的比较器，如果所选位置的校验字的位等于当前地址的对应位。

    Buffer associated with multiple data communication channels
    10.
    发明授权
    Buffer associated with multiple data communication channels 有权
    与多个数据通信通道相关的缓冲区

    公开(公告)号：US06622186B1

    公开(公告)日：2003-09-16

    申请号：US09466508

    申请日：1999-12-17

    申请人： Pascal Moniot ,  Marcello Coppola

    发明人： Pascal Moniot ,  Marcello Coppola

    IPC分类号： G06F1300

    CPC分类号： H04Q11/0478 ,  G06F12/023 ,  G06F12/0875 ,  H04L49/103

    摘要： A buffer for adapting data flows from input channels to output channels is provided. The buffer includes a DRAM organized in blocks and a memory controller for managing assignment of the blocks to the chains of linked blocks. The DRAM contains, as a chain of linked blocks, data associated with each communication channel formed by a pair of input and output channels, and also contains a main queue of free blocks for listing unoccupied blocks. The memory controller includes a cache memory containing a partial queue of free blocks that the memory controller uses in managing block assignment. According to one embodiment, when a level of the partial queue reaches a predetermined minimum limit the cache memory is at least partially filled by a burst from the main queue, and when a level of the partial queue reaches a predetermined maximum limit the cache memory is at least partially emptied by a burst into the main queue. According to another embodiment, the partial queue stores a local image of a top portion of the main queue, and the memory controller exclusively uses the partial queue in assigning blocks to the chains of linked blocks. Further embodiments of the present invention provide methods of managing a buffer.

    摘要翻译： 提供了用于使数据流从输入通道适配到输出通道的缓冲器。 缓冲器包括以块为单位的DRAM，以及存储器控制器，用于管理块链接到链接块的链。 DRAM包含链接块链，与由一对输入和输出通道形成的每个通信通道相关联的数据，并且还包含用于列出未占用块的空闲块的主队列。 存储器控制器包括高速缓冲存储器，其包含存储器控制器在管理块分配中使用的空闲块的部分队列。 根据一个实施例，当部分队列的级别达到预定的最小限度时，高速缓冲存储器至少部分地由来自主队列的突发填充，并且当部分队列的级别达到预定的最大限制时，高速缓存存储器 至少部分地被突发排空到主队列中。 根据另一个实施例，部分队列存储主队列的顶部的本地图像，并且存储器控制器专门使用部分队列将块分配给链接块的链。 本发明的其他实施例提供了管理缓冲器的方法。