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    Longest prefix match lookup using hash function
    2.
    发明申请
    Longest prefix match lookup using hash function 失效
    使用哈希函数的最长前缀匹配查找

    公开(公告)号：US20060173831A1

    公开(公告)日：2006-08-03

    申请号：US11353841

    申请日：2006-02-14

    申请人： Claude Basso ,  Jean Calvignac ,  Gordon Davis ,  Piyush Patel

    发明人： Claude Basso ,  Jean Calvignac ,  Gordon Davis ,  Piyush Patel

    IPC分类号： G06F17/30

    CPC分类号： H04L45/00 ,  G06F17/30985 ,  H04L12/66 ,  H04L45/745 ,  H04L45/7457 ,  Y10S707/99933 ,  Y10S707/99935 ,  Y10S707/99936

    摘要： A method and apparatus are used for finding the longest prefix match in a variable length prefix search when searching a direct table within a routing table structure of a network processor. The search through the routing table structure is expedited by hashing a first segment of an internet protocol address with a virtual private network number followed by concatenating the unhashed bits of the IP address to the result of the hash operation to form an input key. Patterns are compared a bit at a time until an exact match or the best match is found. The search is conducted in a search tree that provides that the matching results will be the best possible match.

    摘要翻译： 当在网络处理器的路由表结构中搜索直接表时，使用方法和装置来在可变长度前缀搜索中找到最长的前缀匹配。 通过路由表结构的搜索是通过用互联网协议地址的第一段与虚拟专用网络号进行散列加速，然后将IP地址的未分配比特连接到散列操作的结果以形成输入密钥。 模式一次比较一点，直到找到完全匹配或最佳匹配。 搜索在搜索树中进行，其提供匹配结果将是最佳匹配。

    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position
    3.
    发明申请
    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position 失效
    网络处理器中的系统方法结构，通过最后一个标志位指示帧分组的最后数据缓冲区，处于第一或第二位置

    公开(公告)号：US20060101172A1

    公开(公告)日：2006-05-11

    申请号：US11320277

    申请日：2005-12-27

    申请人： Claude Basso ,  Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    IPC分类号： G06F5/00

    CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

    摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

    摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

    Data structure supporting session timer and variable aging function including self adjustable 2MSL
    4.
    发明申请
    Data structure supporting session timer and variable aging function including self adjustable 2MSL 审中-公开
    数据结构支持会话定时器和可变老化功能，包括自调节2MSL

    公开(公告)号：US20050050018A1

    公开(公告)日：2005-03-03

    申请号：US10654502

    申请日：2003-09-03

    申请人： Claude Basso ,  Gordon Davis ,  Marco Heddes ,  Dongming Hwang ,  Colin Verrilli

    发明人： Claude Basso ,  Gordon Davis ,  Marco Heddes ,  Dongming Hwang ,  Colin Verrilli

    IPC分类号： G06F17/30

    CPC分类号： G06F16/20

    摘要： Dynamic data search structures are described that are capable of handling large numbers of active entries and a high rate of additions and deletions of active entries while complying with 2MSL requirements and providing precise time-out capabilities. A free queue which is integrated with the timing loop of session entries provides available sessions for new entries in the search structure and removes obsolete sessions from the tree. Multiples of such timing loops can be used to maintain multiple timing intervals. One such timing loop may contain soft entries still attached to the search structure but which are eligible to be removed and to be reused to accommodate new sessions. A spare buffer pool is also included in the data structure to add and remove buffers to maintain delays.

    摘要翻译： 描述了能够处理大量活动条目的动态数据搜索结构，以及符合2MSL要求并提供精确超时能力的活动条目的增加和删除的高速率。 与会话条目的定时循环集成的空闲队列为搜索结构中的新条目提供可用会话，并从树中删除过时的会话。 这种定时循环的倍数可用于维持多个定时间隔。 一个这样的定时循环可以包含仍然附着到搜索结构但是有资格被移除并被重新使用以容纳新会话的软条目。 数据结构中还包括备用缓冲池，以添加和删除缓冲区以维持延迟。

    Method and structure for enqueuing data packets for processing
    6.
    发明申请
    Method and structure for enqueuing data packets for processing 失效
    排队处理数据包的方法和结构

    公开(公告)号：US20060039376A1

    公开(公告)日：2006-02-23

    申请号：US10868725

    申请日：2004-06-15

    申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    IPC分类号： H04L12/56 ,  H04L12/28

    CPC分类号： H04L49/90 ,  H04L49/9042 ,  H04L49/9073 ,  H04L69/22

    摘要： A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.

    摘要翻译： 提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。 网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。 芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。 该方法包括利用报头信息来识别分组的其余部分的位置和范围。 当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时 有空间。

    Structure and method for scheduler pipeline design for hierarchical link sharing
    7.
    发明申请
    Structure and method for scheduler pipeline design for hierarchical link sharing 失效
    用于分层链路共享的调度器流水线设计的结构和方法

    公开(公告)号：US20050177644A1

    公开(公告)日：2005-08-11

    申请号：US10772737

    申请日：2004-02-05

    申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    IPC分类号： G06F15/16 ,  H04L12/56

    CPC分类号： H04L47/60 ,  H04L47/15 ,  H04L47/50 ,  H04L47/52 ,  H04L49/90

    摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.

    摘要翻译： 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

    Method of inserting and deleting leaves in tree table structures
    9.
    发明授权
    Method of inserting and deleting leaves in tree table structures 失效
    在树表结构中插入和删除叶子的方法

    公开(公告)号：US07149749B2

    公开(公告)日：2006-12-12

    申请号：US10453245

    申请日：2003-06-03

    申请人： Claude Basso ,  Jean L. Calvignac ,  Gordon T. Davis ,  Marco Heddes ,  Piyush C. Patel ,  Steven R. Perrin ,  Grayson W. Randall ,  Sonia K. Rovner

    发明人： Claude Basso ,  Jean L. Calvignac ,  Gordon T. Davis ,  Marco Heddes ,  Piyush C. Patel ,  Steven R. Perrin ,  Grayson W. Randall ,  Sonia K. Rovner

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30625 ,  Y10S707/99936 ,  Y10S707/99942 ,  Y10S707/99943

    摘要： A technique is provided to either insert or delete a leaf in a Patricia tree having a direct table and a plurality of PSCB's which decode portions of the pattern of a leaf in the tree without shutting down the functioning of the tree. A leaf having a pattern is identified as either a leaf to be inserted or deleted. Using the pattern, the tree is walked once to identify the location of the leaf to be deleted or the location where the leaf is to be inserted. If it is a delete operation, the leaf to be deleted is identified and deleted, and any relevant PSCB modified, if necessary. If it is an insert operation, the tree is walked a second time to insert the leaf and reform or create any PSCB in the chain that needs to be reformed or created. The technique also is applicable to inserting or deleting a prefix of a prefix.

    摘要翻译： 提供了一种技术来插入或删除具有直接表的Patricia树中的叶子，以及多个PSCB，其解码树中的叶子的图案的部分，而不关闭树的功能。 具有图案的叶被识别为要插入或删除的叶。 使用图案，树一次走一次，以确定要删除的叶的位置或叶被插入的位置。 如果是删除操作，则要删除的叶被识别和删除，并且必要时修改任何相关的PSCB。 如果是插入操作，则树第二次移动以插入叶，并在需要重新创建或创建的链中重新构建或创建任何PSCB。 该技术也适用于插入或删除前缀的前缀。

    Multi-bit Patricia trees
    10.
    发明授权
    Multi-bit Patricia trees 失效
    多比特Patricia树

    公开(公告)号：US06963868B2

    公开(公告)日：2005-11-08

    申请号：US10448528

    申请日：2003-05-30

    申请人： Claude Basso ,  Jean L. Calvignac ,  Gordon T. Davis ,  Marco Heddes ,  Piyush C. Patel ,  Steven R. Perrin ,  Grayson W. Randall

    发明人： Claude Basso ,  Jean L. Calvignac ,  Gordon T. Davis ,  Marco Heddes ,  Piyush C. Patel ,  Steven R. Perrin ,  Grayson W. Randall

    IPC分类号： G06F7/00 ,  G06F17/30

    CPC分类号： H04L45/00 ,  H04L45/56 ,  H04L45/7457 ,  Y10S707/99933

    摘要： A tree structure and method to organize routing information for processing messages within a network, each message being associated with a search key of “n” bits. The processing determines where to send the message next. The structure has a direct table (DT) of 2x entries for decoding the first “x” bits of the search key, and one or more pattern search control blocks (PSCB's), each having 2m entries for decoding subsequent groups of “m” bits. Each PSCB entry and DT entry includes a pointer to data associated with a specific route, if at this point a specific routing table entry is a potential match to the search key or a pointer to a subsequent PSCB if the end of a search trail is not identified. Each PSCB entry DT entry also indicates that the search has been resolved to the end of the search trail.

    摘要翻译： 一种用于组织用于处理网络内的消息的路由信息​​的树结构和方法，每个消息与“n”比特的搜索关键字相关联。 该处理确定接下来发送消息的位置。 该结构具有用于对搜索关键字的第一个“x”比特进行解码的2个“<”条目的直接表（DT），以及一个或多个模式搜索控制块（PSCB），每个具有2个