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37 条记录 (耗时 0.041 秒)

    Longest prefix match lookup using hash function
    2.
    发明申请
    Longest prefix match lookup using hash function 失效
    使用哈希函数的最长前缀匹配查找

    公开(公告)号：US20060173831A1

    公开(公告)日：2006-08-03

    申请号：US11353841

    申请日：2006-02-14

    申请人： Claude Basso ,  Jean Calvignac ,  Gordon Davis ,  Piyush Patel

    发明人： Claude Basso ,  Jean Calvignac ,  Gordon Davis ,  Piyush Patel

    IPC分类号： G06F17/30

    CPC分类号： H04L45/00 ,  G06F17/30985 ,  H04L12/66 ,  H04L45/745 ,  H04L45/7457 ,  Y10S707/99933 ,  Y10S707/99935 ,  Y10S707/99936

    摘要： A method and apparatus are used for finding the longest prefix match in a variable length prefix search when searching a direct table within a routing table structure of a network processor. The search through the routing table structure is expedited by hashing a first segment of an internet protocol address with a virtual private network number followed by concatenating the unhashed bits of the IP address to the result of the hash operation to form an input key. Patterns are compared a bit at a time until an exact match or the best match is found. The search is conducted in a search tree that provides that the matching results will be the best possible match.

    摘要翻译： 当在网络处理器的路由表结构中搜索直接表时，使用方法和装置来在可变长度前缀搜索中找到最长的前缀匹配。 通过路由表结构的搜索是通过用互联网协议地址的第一段与虚拟专用网络号进行散列加速，然后将IP地址的未分配比特连接到散列操作的结果以形成输入密钥。 模式一次比较一点，直到找到完全匹配或最佳匹配。 搜索在搜索树中进行，其提供匹配结果将是最佳匹配。

    Method and system for compressing multi-field rule specifications
    3.
    发明申请
    Method and system for compressing multi-field rule specifications 失效
    压缩多场规则规范的方法和系统

    公开(公告)号：US20050237938A1

    公开(公告)日：2005-10-27

    申请号：US10832957

    申请日：2004-04-27

    申请人： Everett Corl ,  Gordon Davis ,  Marco Heddes ,  Piyush Patel ,  Ravinder Sabhikhi

    发明人： Everett Corl ,  Gordon Davis ,  Marco Heddes ,  Piyush Patel ,  Ravinder Sabhikhi

    IPC分类号： G01R31/08 ,  G06F11/00 ,  G06F15/18 ,  G06F17/00 ,  G06N5/02 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26

    CPC分类号： G06N99/005

    摘要： The present invention relates to a method and system for storing a plurality of multi-field classification rules in a computer system. Each multi-field classification rule includes a rule specification that itself includes a plurality of fields and a plurality of field definitions corresponding to the fields. The method of the present invention includes providing a virtual rule table, where the table stores a plurality of field definitions, and for each of the plurality of multi-field classification rules, compressing the rule specification by replacing at least one field definition with an associated index into the virtual rule table. The method also includes storing each of the compressed rule specifications and the virtual rule table in a shared segment of memory.

    摘要翻译： 本发明涉及一种用于在计算机系统中存储多个多场分类规则的方法和系统。 每个多字段分类规则包括本身包括多个字段的规则规范和对应于字段的多个字段定义。 本发明的方法包括提供虚拟规则表，其中表存储多个字段定义，并且对于多个多字段分类规则中的每一个，通过用相关联的替换来替换至少一个字段定义来压缩规则规范 索引到虚拟规则表。 该方法还包括将每个压缩规则规范和虚拟规则表存储在存储器的共享段中。

    Method and system for managing multi-field classification rules relating to ingress contexts and egress contexts
    4.
    发明申请
    Method and system for managing multi-field classification rules relating to ingress contexts and egress contexts 失效
    用于管理与入口上下文和出口上下文相关的多字段分类规则的方法和系统

    公开(公告)号：US20050237939A1

    公开(公告)日：2005-10-27

    申请号：US10832958

    申请日：2004-04-27

    申请人： Everett Corl ,  Gordon Davis ,  Marco Heddes ,  Piyush Patel ,  Ravinder Sabhikhi

    发明人： Everett Corl ,  Gordon Davis ,  Marco Heddes ,  Piyush Patel ,  Ravinder Sabhikhi

    IPC分类号： G06F15/00 ,  G06F15/18 ,  G06F17/00 ,  G06N5/02 ,  G06N99/00 ,  H04J3/14 ,  H04L12/26 ,  G06N1/00

    CPC分类号： G06N99/005

    摘要： The present invention relates to a method and system for managing a plurality of multi-field classification rules. The method includes providing a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and providing a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The method also includes utilizing the first table and the second table to identify any rules relating to the ingress context and any rules relating to the egress context that match a search key.

    摘要翻译： 本发明涉及一种用于管理多个多场分类规则的方法和系统。 该方法包括提供第一表格，该第一表格包括对应于与入口上下文有关的多个规则的多个条目，并提供第二表格，该第二表格包括对应于与出口上下文有关的多个规则的多个条目。 该方法还包括利用第一表和第二表来识别与入口上下文有关的任何规则以及与搜索关键字匹配的出口上下文相关的任何规则。

    Data structure supporting session timer and variable aging function including self adjustable 2MSL
    6.
    发明申请
    Data structure supporting session timer and variable aging function including self adjustable 2MSL 审中-公开
    数据结构支持会话定时器和可变老化功能，包括自调节2MSL

    公开(公告)号：US20050050018A1

    公开(公告)日：2005-03-03

    申请号：US10654502

    申请日：2003-09-03

    申请人： Claude Basso ,  Gordon Davis ,  Marco Heddes ,  Dongming Hwang ,  Colin Verrilli

    发明人： Claude Basso ,  Gordon Davis ,  Marco Heddes ,  Dongming Hwang ,  Colin Verrilli

    IPC分类号： G06F17/30

    CPC分类号： G06F16/20

    摘要： Dynamic data search structures are described that are capable of handling large numbers of active entries and a high rate of additions and deletions of active entries while complying with 2MSL requirements and providing precise time-out capabilities. A free queue which is integrated with the timing loop of session entries provides available sessions for new entries in the search structure and removes obsolete sessions from the tree. Multiples of such timing loops can be used to maintain multiple timing intervals. One such timing loop may contain soft entries still attached to the search structure but which are eligible to be removed and to be reused to accommodate new sessions. A spare buffer pool is also included in the data structure to add and remove buffers to maintain delays.

    摘要翻译： 描述了能够处理大量活动条目的动态数据搜索结构，以及符合2MSL要求并提供精确超时能力的活动条目的增加和删除的高速率。 与会话条目的定时循环集成的空闲队列为搜索结构中的新条目提供可用会话，并从树中删除过时的会话。 这种定时循环的倍数可用于维持多个定时间隔。 一个这样的定时循环可以包含仍然附着到搜索结构但是有资格被移除并被重新使用以容纳新会话的软条目。 数据结构中还包括备用缓冲池，以添加和删除缓冲区以维持延迟。

    NETWORK PROCESSOR WITH SINGLE INTERFACE SUPPORTING TREE SEARCH ENGINE AND CAM
    7.
    发明申请
    NETWORK PROCESSOR WITH SINGLE INTERFACE SUPPORTING TREE SEARCH ENGINE AND CAM 失效
    网络处理器，具有单接口支持树搜索引擎和CAM

    公开(公告)号：US20060265363A1

    公开(公告)日：2006-11-23

    申请号：US11457952

    申请日：2006-07-17

    申请人： Jean Calvignac ,  Gordon Davis ,  Marco Heddes ,  Michael Siegel

    发明人： Jean Calvignac ,  Gordon Davis ,  Marco Heddes ,  Michael Siegel

    IPC分类号： G06F17/30

    CPC分类号： H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

    摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

    摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。

    Method and structure for enqueuing data packets for processing
    9.
    发明申请
    Method and structure for enqueuing data packets for processing 失效
    排队处理数据包的方法和结构

    公开(公告)号：US20060039376A1

    公开(公告)日：2006-02-23

    申请号：US10868725

    申请日：2004-06-15

    申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    IPC分类号： H04L12/56 ,  H04L12/28

    CPC分类号： H04L49/90 ,  H04L49/9042 ,  H04L49/9073 ,  H04L69/22

    摘要： A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.

    摘要翻译： 提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。 网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。 芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。 该方法包括利用报头信息来识别分组的其余部分的位置和范围。 当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时 有空间。

    Structure and method for scheduler pipeline design for hierarchical link sharing
    10.
    发明申请
    Structure and method for scheduler pipeline design for hierarchical link sharing 失效
    用于分层链路共享的调度器流水线设计的结构和方法

    公开(公告)号：US20050177644A1

    公开(公告)日：2005-08-11

    申请号：US10772737

    申请日：2004-02-05

    申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    IPC分类号： G06F15/16 ,  H04L12/56

    CPC分类号： H04L47/60 ,  H04L47/15 ,  H04L47/50 ,  H04L47/52 ,  H04L49/90

    摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.

    摘要翻译： 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。