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    Method and system for managing multi-field classification rules relating to ingress contexts and egress contexts
    1.
    发明申请
    Method and system for managing multi-field classification rules relating to ingress contexts and egress contexts 失效
    用于管理与入口上下文和出口上下文相关的多字段分类规则的方法和系统

    公开(公告)号：US20050237939A1

    公开(公告)日：2005-10-27

    申请号：US10832958

    申请日：2004-04-27

    申请人： Everett Corl ,  Gordon Davis ,  Marco Heddes ,  Piyush Patel ,  Ravinder Sabhikhi

    发明人： Everett Corl ,  Gordon Davis ,  Marco Heddes ,  Piyush Patel ,  Ravinder Sabhikhi

    IPC分类号： G06F15/00 ,  G06F15/18 ,  G06F17/00 ,  G06N5/02 ,  G06N99/00 ,  H04J3/14 ,  H04L12/26 ,  G06N1/00

    CPC分类号： G06N99/005

    摘要： The present invention relates to a method and system for managing a plurality of multi-field classification rules. The method includes providing a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and providing a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The method also includes utilizing the first table and the second table to identify any rules relating to the ingress context and any rules relating to the egress context that match a search key.

    摘要翻译： 本发明涉及一种用于管理多个多场分类规则的方法和系统。 该方法包括提供第一表格，该第一表格包括对应于与入口上下文有关的多个规则的多个条目，并提供第二表格，该第二表格包括对应于与出口上下文有关的多个规则的多个条目。 该方法还包括利用第一表和第二表来识别与入口上下文有关的任何规则以及与搜索关键字匹配的出口上下文相关的任何规则。

    Method and system for compressing multi-field rule specifications
    2.
    发明申请
    Method and system for compressing multi-field rule specifications 失效
    压缩多场规则规范的方法和系统

    公开(公告)号：US20050237938A1

    公开(公告)日：2005-10-27

    申请号：US10832957

    申请日：2004-04-27

    申请人： Everett Corl ,  Gordon Davis ,  Marco Heddes ,  Piyush Patel ,  Ravinder Sabhikhi

    发明人： Everett Corl ,  Gordon Davis ,  Marco Heddes ,  Piyush Patel ,  Ravinder Sabhikhi

    IPC分类号： G01R31/08 ,  G06F11/00 ,  G06F15/18 ,  G06F17/00 ,  G06N5/02 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26

    CPC分类号： G06N99/005

    摘要： The present invention relates to a method and system for storing a plurality of multi-field classification rules in a computer system. Each multi-field classification rule includes a rule specification that itself includes a plurality of fields and a plurality of field definitions corresponding to the fields. The method of the present invention includes providing a virtual rule table, where the table stores a plurality of field definitions, and for each of the plurality of multi-field classification rules, compressing the rule specification by replacing at least one field definition with an associated index into the virtual rule table. The method also includes storing each of the compressed rule specifications and the virtual rule table in a shared segment of memory.

    摘要翻译： 本发明涉及一种用于在计算机系统中存储多个多场分类规则的方法和系统。 每个多字段分类规则包括本身包括多个字段的规则规范和对应于字段的多个字段定义。 本发明的方法包括提供虚拟规则表，其中表存储多个字段定义，并且对于多个多字段分类规则中的每一个，通过用相关联的替换来替换至少一个字段定义来压缩规则规范 索引到虚拟规则表。 该方法还包括将每个压缩规则规范和虚拟规则表存储在存储器的共享段中。

    Longest prefix match (LPM) algorithm implementation for a network processor
    5.
    发明申请
    Longest prefix match (LPM) algorithm implementation for a network processor 失效
    用于网络处理器的最长前缀匹配（LPM）算法实现

    公开(公告)号：US20050144553A1

    公开(公告)日：2005-06-30

    申请号：US11045634

    申请日：2005-01-28

    申请人： Brian Bass ,  Jean Calvignac ,  Marco Heddes ,  Antonios Maragkos ,  Piyush Patel ,  Michael Siegel ,  Fabrice Verplanken

    发明人： Brian Bass ,  Jean Calvignac ,  Marco Heddes ,  Antonios Maragkos ,  Piyush Patel ,  Michael Siegel ,  Fabrice Verplanken

    IPC分类号： G06F17/30 ,  G06F17/00

    CPC分类号： G06F17/30985 ,  H04L45/7457 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99936 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99945

    摘要： Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first: match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.

    摘要翻译： 当搜索具有可变长度模式或前缀的表时，用于查找最长前缀的新型数据结构，方法和装置匹配搜索。 要找到完全匹配或最佳匹配前缀，模式必须一次比较一下，直到找到完全匹配或第一个匹配。 这需要“n”个比较或存储器访问来识别最接近的匹配模式。 树的建立方式使得匹配结果保证是最佳匹配，无论是完全匹配还是最长匹配前缀。 使用所有鸟的踪迹和相关的前缀长度可以确定路线中正确的前缀结果。 通过构建，搜索树在步道或树的步行期间在第一次比较之前或之后提供最佳的匹配前缀。

    Full match (FM) search algorithm implementation for a network processor
    6.
    发明申请
    Full match (FM) search algorithm implementation for a network processor 失效
    网络处理器的完全匹配（FM）搜索算法实现

    公开(公告)号：US20050076010A1

    公开(公告)日：2005-04-07

    申请号：US10650327

    申请日：2003-08-28

    申请人： Brian Bass ,  Jean Calvignac ,  Marco Heddes ,  Antonios Maragkos ,  Piyush Patel ,  Michael Siegel ,  Fabrice Verplanken

    发明人： Brian Bass ,  Jean Calvignac ,  Marco Heddes ,  Antonios Maragkos ,  Piyush Patel ,  Michael Siegel ,  Fabrice Verplanken

    IPC分类号： G06F17/30 ,  H04L12/46 ,  H04L12/56 ,  G06F7/00

    CPC分类号： H04L45/742 ,  H04L45/7453 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99937 ,  Y10S707/99943 ,  Y10S707/99945

    摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBS) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.

    摘要翻译： 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 输入密钥，对密钥执行散列函数，访问直接表（DT），并通过模式搜索控制块（PSCBS）走树，直到到达叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。 用于存储散列键和树中相关信息的数据结构称为叶。 每个叶对应于与输入键完全匹配的单个键。 叶包含关键以及其他信息。 叶片的长度是可编程的，密钥的长度也是可编程的。 叶存储在随机存取存储器中，并被实现为单个存储器条目。 如果键位于直接表中，则称为直接叶。

    Controller for multiple instruction thread processors
    8.
    发明申请
    Controller for multiple instruction thread processors 失效
    多指令线程处理器的控制器

    公开(公告)号：US20050022196A1

    公开(公告)日：2005-01-27

    申请号：US10915983

    申请日：2004-08-11

    申请人： Gordon Davis ,  Marco Heddes ,  Ross Leavens ,  Fabrice Verplanken

    发明人： Gordon Davis ,  Marco Heddes ,  Ross Leavens ,  Fabrice Verplanken

    IPC分类号： G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F9/52 ,  G06F15/16

    CPC分类号： G06F9/3802 ,  G06F9/3851

    摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.

    摘要翻译： 机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。

    Network processing system, core language processor and method of executing a sequence of instructions in a stored program
    9.
    发明申请
    Network processing system, core language processor and method of executing a sequence of instructions in a stored program 审中-公开
    网络处理系统，核心语言处理器和在存储的程序中执行指令序列的方法

    公开(公告)号：US20050033938A1

    公开(公告)日：2005-02-10

    申请号：US10940434

    申请日：2004-09-14

    申请人： Gordon Davis ,  Marco Heddes ,  Ross Leavens ,  Mark Rinaldi

    发明人： Gordon Davis ,  Marco Heddes ,  Ross Leavens ,  Mark Rinaldi

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F15/00

    CPC分类号： G06F9/3013 ,  G06F9/30087 ,  G06F9/3885

    摘要： A network processor utilizes protocol processor units (PPUs) to provide instruction communication for the network. Each PPU includes a core language processor (CLP). Each CLP contains general purpose registers and includes a coprocessor that contains scalar registers and array registers. The CLP controls and instructs a plurality of coprocessors that run in parallel with the CLP. Each coprocessor is a specialized hardware assist engine having direct access to the CLP registers and arrays through two sets of interface signals, a coprocessor execution interface and a coprocessor data interface.

    摘要翻译： 网络处理器利用协议处理器单元（PPU）为网络提供指令通信。 每个PPU包括核心语言处理器（CLP）。 每个CLP都包含通用寄存器，包括一个包含标量寄存器和数组寄存器的协处理器。 CLP控制并指示与CLP并行运行的多个协处理器。 每个协处理器是专门的硬件辅助引擎，可以通过两组接口信号，协处理器执行接口和协处理器数据接口直接访问CLP寄存器和阵列。

    Data structure supporting random delete and aging/timer function
    10.
    发明申请
    Data structure supporting random delete and aging/timer function 失效
    数据结构支持随机删除和老化/定时器功能

    公开(公告)号：US20050050188A1

    公开(公告)日：2005-03-03

    申请号：US10654139

    申请日：2003-09-03

    申请人： Gordon Davis ,  Marco Heddes ,  Dongming Hwang

    发明人： Gordon Davis ,  Marco Heddes ,  Dongming Hwang

    IPC分类号： G06F15/173 ,  G06F17/30

    CPC分类号： G06F17/30955 ,  Y10S707/99933 ,  Y10S707/99942

    摘要： A procedure is used to provide data structures that handle large numbers of active data entries and a high rate of additions and deletions of active entries. The procedure utilizes one or more of the following modifications. Timers are removed from individual session table entries and are linked via pointers. Bilateral links are established between the session table and the timer structure. Aging/timer checks are applied to the timer control block (TCB). A chain of TCBs, optionally including an excess of blocks, may be used along with packing of multiple TCBs into a single memory location. This excess of blocks permits a terminated session to continue to occupy a TCB until the timer process progresses to that block location in the chain of blocks.

    摘要翻译： 一个过程用于提供处理大量活动数据条目的数据结构以及高活动条目的添加和删除率。 该过程利用以下一个或多个修改。 定时器从单个会话表条目中删除，并通过指针进行链接。 在会话表和定时器结构之间建立双向链路。 老化/定时器检查应用于定时器控制块（TCB）。 可以使用可选地包括多余块的TCB链，以及将多个TCB打包到单个存储器位置中。 这个多余的块允许终止的会话继续占用TCB，直到定时器进程前进到块链中的块位置。