公开(公告)号：US06232214B1

公开(公告)日：2001-05-15

申请号：US09316475

申请日：1999-05-21

申请人： Claymens Lee ,  Gary Hong

发明人： Claymens Lee ,  Gary Hong

IPC分类号： H01L214763

CPC分类号： H01L21/7682

摘要： A method for fabricating an inter-metal dielectric layer. Several conducting wires are formed on a substrate, and openings lie between the adjacent conducting wires. A first dielectric layer fills the openings, and the surface of the first dielectric layer is lower than that of the conducting wires. A spacer is formed on a sidewall of each of the conducting wires. The first dielectric layer is removed to expose the bottom of the spacer. A second dielectric layer is formed to cover the conducting wires.

摘要翻译： 一种制造金属间介电层的方法。 在基板上形成几根导线，开口位于相邻的导线之间。 第一电介质层填充开口，并且第一电介质层的表面低于导线的表面。 在每个导线的侧壁上形成间隔物。 去除第一介电层以露出间隔物的底部。 形成第二电介质层以覆盖导线。

公开(公告)号：US6153471A

公开(公告)日：2000-11-28

申请号：US313511

申请日：1999-05-17

申请人： Claymens Lee ,  Gary Hong

发明人： Claymens Lee ,  Gary Hong

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory. After the formation of a trench isolation structure, openings are formed, in a direction perpendicular to the orientation of the trench isolation structure, in order to form a buried bit line. A spacer is formed on the opening sidewall of the bit line in which the distance between a top of the spacer and the interface of a substrate and a pad oxide layer is the depth of the source/drain region. The opening is then filled with a doped polysilicon conducting layer used as the buried bit line. The dopant from the polysilicon conducting layer is driven into the substrate to form the source/drain region.

摘要翻译： 一种制造闪速存储器的方法。 在形成沟槽隔离结构之后，在垂直于沟槽隔离结构的取向的方向上形成开口，以便形成掩埋位线。 间隔物形成在位线的开口侧壁上，其中间隔物的顶部与衬底和衬垫氧化物层的界面之间的距离是源极/漏极区域的深度。 然后用用作掩埋位线的掺杂多晶硅导电层填充开口。 来自多晶硅导电层的掺杂剂被驱动到衬底中以形成源极/漏极区域。

公开(公告)号：US6150276A

公开(公告)日：2000-11-21

申请号：US313166

申请日：1999-05-17

申请人： Claymens Lee ,  Gary Hong

发明人： Claymens Lee ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/49 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L29/6659 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/6656

摘要： A method for fabricating a metal-oxide semiconductor (MOS) transistor on a semiconductor substrate is described. The invention introduces an air chamber with a low dielectric constant between the gate and the source/drain region so as to lower the fringing electric field between the gate and the source/drain region. Moreover, the dielectric constant of the dielectric layer between the gate and the source/drain region is reduced. Therefore, the gate-to-drain capacitance is decreased in the MOS transistor.

摘要翻译： 描述了在半导体衬底上制造金属氧化物半导体（MOS）晶体管的方法。 本发明在栅极和源极/漏极区域之间引入具有低介电常数的气室，以便降低栅极和源极/漏极区域之间的边缘电场。 此外，栅极和源极/漏极区域之间的介电层的介电常数降低。 因此，MOS晶体管中的栅 - 漏电容减小。

公开(公告)号：US06277697B1

公开(公告)日：2001-08-21

申请号：US09439032

申请日：1999-11-12

申请人： Claymens Lee

发明人： Claymens Lee

IPC分类号： H01L21336

CPC分类号： H01L21/823481 ,  H01L21/76237 ,  H01L27/10844

摘要： A method to reduce the inverse-narrow-line-effect is described in which an active region and an isolation region are defined on a substrate. A doped region is formed adjacent to the substrate surface, wherein the area of the doped region includes the isolation region and the edge of the active region. The depth of the doped region is shallower than that of the source/drain region formed subsequently. A shallow trench is formed thereafter in the isolation region adjacent to the active region, such that the doped region located in the substrate at the edge of the active region is retained. A liner oxide layer is further formed on the inner wall of the shallow trench. An oxide layer, which is as high as the surface of the cap layer, is formed to fill the trench. After the removal of the pad oxide layer and the cap layer, a gate oxide layer and a gate are formed on the substrate.

摘要翻译： 描述了减少反向窄线效应的方法，其中在衬底上限定有源区和隔离区。 掺杂区域邻近衬底表面形成，其中掺杂区域的区域包括隔离区域和有源区域的边缘。 掺杂区域的深度比随后形成的源极/漏极区域的深度浅。 此后在与有源区相邻的隔离区中形成浅沟槽，使得位于有源区的边缘处的衬底中的掺杂区被保留。 衬底氧化物层进一步形成在浅沟槽的内壁上。 形成与盖层的表面一样高的氧化物层，以填充沟槽。 在去除焊盘氧化物层和覆盖层之后，在衬底上形成栅极氧化物层和栅极。

公开(公告)号：US06238987B1

公开(公告)日：2001-05-29

申请号：US09394636

申请日：1999-09-13

申请人： Claymens Lee

发明人： Claymens Lee

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L29/4966 ,  H01L29/6659

摘要： A method to lower the parasitic capacitance is described, in which a low dielectric constant air-gap is formed in the dielectric layers at both sides of the gate to lower the parasitic capacitance present between the gate and the source/drain region. The air-gap is formed by forming spacers at both sides of the gate, followed by forming a first dielectric layer with its height lower than the top of the spacers. Thereafter, the spacers are removed by wet etching to form a hole with its top narrower than its bottom. A second dielectric layer is further formed, by a deposition technique with a weaker step coverage capability, to encapsulate the hole and to cover the substrate, wherein the encapsulated hole is the air-gap.

摘要翻译： 描述了降低寄生电容的方法，其中在栅极两侧的电介质层中形成低介电常数气隙，以降低存在于栅极和源极/漏极区域之间的寄生电容。 通过在栅极的两侧形成间隔物，然后形成其高度低于间隔物的顶部的第一介电层，形成气隙。 此后，通过湿蚀刻除去间隔物，以形成其顶部比其底部窄的孔。 通过具有较弱的台阶覆盖能力的沉积技术进一步形成第二电介质层，以封装孔并覆盖衬底，其中封装的孔是气隙。

公开(公告)号：US06804204B2

公开(公告)日：2004-10-12

申请号：US09815131

申请日：2001-03-22

申请人： Claymens Lee ,  Jean-Ming Lee

发明人： Claymens Lee ,  Jean-Ming Lee

IPC分类号： H04B330

CPC分类号： H04B3/23

摘要： An apparatus of a digital echo canceller and method therefor, a designed selector is used values of receiving and input signals to estimate the length of a cable. The response values of an insignificant part of the echo signal can be selected. Multiplication and addition operations are carried out in a response region of a significant part of the echo signal. An estimated echo signal is produced to cancel the echo signal, unnecessary operations and the cost of a hardware can be reduced.

摘要翻译： 数字回声消除器的装置及其方法，设计的选择器使用接收和输入信号的值来估计电缆的长度。 可以选择回波信号无效部分的响应值。 在回波信号的大部分的响应区域中进行乘法和加法运算。 产生估计的回波信号以消除回波信号，可以减少不必要的操作和硬件的成本。

公开(公告)号：US06251750B1

公开(公告)日：2001-06-26

申请号：US09396140

申请日：1999-09-15

申请人： Claymens Lee

发明人： Claymens Lee

IPC分类号： H01L2176

CPC分类号： H01L21/76235 ,  H01L21/76205

摘要： A method of manufacturing a shallow trench isolation in a substrate. The substrate has a pad oxide layer and a mask layer formed thereon in sequence and a trench penetrating through the mask layer and the pad oxide layer and into the substrate. A thermal oxidation process is performed to form a liner oxide layer on a portion of the substrate exposed by the trench. A spacer is formed on the sidewall of the mask layer, the pad oxide layer and the trench. An oxidation process is performed to oxidize a portion of the substrate under a portion of the liner oxide layer located on the bottom of the trench. An insulating layer is formed over the substrate and filling the trench. A planarization process is performed to remove a portion of the insulating layer until the mask layer is exposed. The mask layer and the pad oxide layer are removed.

摘要翻译： 一种在衬底中制造浅沟槽隔离的方法。 衬底具有依次形成在其上的衬垫氧化物层和掩模层，以及穿过掩模层和焊盘氧化物层并进入衬底的沟槽。 进行热氧化处理以在由沟槽暴露的衬底的一部分上形成衬垫氧化物层。 在掩模层，焊盘氧化物层和沟槽的侧壁上形成间隔物。 执行氧化处理以在位于沟槽底部的衬垫氧化物层的一部分下氧化衬底的一部分。 绝缘层形成在衬底上并填充沟槽。 执行平面化处理以去除绝缘层的一部分直到掩模层暴露。 去除掩模层和焊盘氧化物层。

公开(公告)号：US07280493B2

公开(公告)日：2007-10-09

申请号：US10064238

申请日：2002-06-25

申请人： Claymens Lee

发明人： Claymens Lee

IPC分类号： H04B3/20

CPC分类号： H04B3/23

摘要： The present invention provides a method for hardware reduction in the echo canceller and the near-end crosstalk canceller. The method applies an N (N is a positive integer) times divide frequency sampling operation onto the input data list of the echo canceller first (and the near-end crosstalk canceller). Then, it applies an N times multiply frequency sampling operation onto the output data list of the echo canceller (and the near-end crosstalk canceller) to generate a multiplied frequency data list. Afterwards, a low pass filter operation is applied to the multiplied frequency data list to generate a low pass data list to eliminate the echo signal (and the near-end crosstalk signal). The present invention reduces the number of the taps in the echo canceller and the near-end crosstalk canceller by using the digital signal process technique. Therefore, the area of the whole communication IC occupied by the echo canceller and the near-end crosstalk canceller can be reduced.

摘要翻译： 本发明提供一种用于回波消除器和近端串扰消除器中的硬件减少的方法。 该方法将N（N为正整数）倍的分频频率采样操作应用于首先回波消除器的输入数据列表（和近端串扰消除器）。 然后，对回波消除器（和近端串扰消除器）的输出数据列表应用N次倍频采样操作，生成倍频数据列表。 然后，将低通滤波器操作应用于倍频数据列表以产生低通数据列表以消除回波信号（和近端串扰信号）。 本发明通过使用数字信号处理技术来减少回波消除器和近端串扰消除器中的抽头的数量。 因此，可以减少由回波消除器和近端串扰消除器占用的整个通信IC的面积。

公开(公告)号：US06221725B1

公开(公告)日：2001-04-24

申请号：US09286004

申请日：1999-04-05

申请人： Claymens Lee

发明人： Claymens Lee

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L29/665

摘要： A method of fabricating a silicide layer on a gate electrode is described. A gate oxide layer is formed on a substrate. A gate electrode is formed on a portion of the gate oxide layer. A spacer is formed on a sidewall of the gate electrode to cover the other portion of the gate oxide layer. The spacer is removed to expose a portion of the gate oxide layer. A metallic layer is formed over the substrate to cover the gate electrode and the gate oxide layer. An annealing step is performed to transform the metallic layer in contact with the gate electrode and the source/drain region into a silicide layer. The remaining metallic layer is removed.

摘要翻译： 描述了在栅电极上制造硅化物层的方法。 栅极氧化层形成于基板上。 栅电极形成在栅氧化层的一部分上。 在栅电极的侧壁上形成间隔物以覆盖栅极氧化物层的另一部分。 去除间隔物以露出栅极氧化物层的一部分。 在衬底上形成金属层以覆盖栅极电极和栅极氧化物层。 执行退火步骤以将与栅极电极和源极/漏极区域接触的金属层变换为硅化物层。 剩下的金属层被去除。

公开(公告)号：US6096623A

公开(公告)日：2000-08-01

申请号：US392924

申请日：1999-09-09

申请人： Claymens Lee

发明人： Claymens Lee

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76213 ,  H01L21/76237

摘要： A method for forming a shallow trench isolation structure. A pad oxide layer is formed over a substrate. A hard mask layer is formed over the pad oxide layer. A portion of the hard mask layer, the pad oxide layer and the substrate is removed to form a trench in the substrate. Insulation material is deposited into the trench to form an insulation plug. The hard mask layer is removed to expose the sidewalls of the insulation plug. Spacers are formed on the exposed sidewalls of the insulation plug. Ions are implanted into the substrate. The pad oxide layer, the spacers and a portion of the insulation plug are removed. Finally, a gate oxide layer thicker in region around the edge of the insulation plug is formed over the substrate by oxidation.

摘要翻译： 一种形成浅沟槽隔离结构的方法。 在衬底上形成衬垫氧化物层。 在衬垫氧化物层上形成硬掩模层。 去除硬掩模层，衬垫氧化物层和衬底的一部分以在衬底中形成沟槽。 将绝缘材料沉积到沟槽中以形成绝缘塞。 去除硬掩模层以暴露绝缘塞的侧壁。 间隔件形成在绝缘塞的暴露的侧壁上。 离子植入衬底。 衬垫氧化物层，间隔物和绝缘插头的一部分被去除。 最后，通过氧化在衬底上形成在绝缘插头的边缘附近的区域中较厚的栅氧化层。