公开(公告)号：US20170272085A1

公开(公告)日：2017-09-21

申请号：US15479691

申请日：2017-04-05

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Peter Vlasenko ,  Dieter Haerle

IPC: H03L7/081 ,  H03L7/10 ,  H03L7/089 ,  H03L7/095

CPC classification number: H03L7/081 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

公开(公告)号：USRE47715E1

公开(公告)日：2019-11-05

申请号：US14334347

申请日：2014-07-17

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Dieter Haerle

IPC: H03L7/06 ,  H03L7/089 ,  H03L7/081

Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

公开(公告)号：US10122369B2

公开(公告)日：2018-11-06

申请号：US15479691

申请日：2017-04-05

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Peter Vlasenko ,  Dieter Haerle

IPC: H03L7/08 ,  H03L7/081 ,  H03L7/10 ,  H03L7/089 ,  H03L7/095

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

公开(公告)号：US20140225651A1

公开(公告)日：2014-08-14

申请号：US14257635

申请日：2014-04-21

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/10

Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

Abstract translation: 延迟锁定环包括初始化电路，其确保将DLL初始化为不接近延迟与控制电压特性的任一端的工作点。 初始化电路强制DLL最初从初始延迟开始搜索锁定点，延迟在一个方向上变化，迫使DLL跳过第一个锁定点。 初始化电路仅允许DLL改变从初始延迟到达到工作点的一个方向的电压控制延迟环的延迟。