Backlit Photodiode and Method of Manufacturing a Backlit Photodiode
    1.
    发明申请
    Backlit Photodiode and Method of Manufacturing a Backlit Photodiode 有权
    背光光电二极管及制造背光光电二极管的方法

    公开(公告)号:US20070138588A1

    公开(公告)日:2007-06-21

    申请号:US11609934

    申请日:2006-12-13

    IPC分类号: H01L31/00 H01L21/00

    CPC分类号: H01L31/022408

    摘要: A backlit photodiode array includes a semiconductor substrate having first and second main surfaces opposite to each other. A first dielectric layer is formed on the first main surface. First and second conductive vias are formed extending from the second main surface through the semiconductor substrate and the first dielectric layer. The first and second conductive vias are isolated from the semiconductor substrate by a second dielectric material. A first anode/cathode layer of a first conductivity is formed on the first dielectric layer and is electrically coupled to the first conductive via. An intrinsic semiconductor layer is formed on the first anode/cathode layer. A second anode/cathode layer of a second conductivity opposite to the first conductivity is formed on the intrinsic semiconductor layer and is electrically coupled to the second conductive via.

    摘要翻译: 背光光电二极管阵列包括具有彼此相对的第一和第二主表面的半导体衬底。 第一介电层形成在第一主表面上。 第一和第二导电通孔从第二主表面延伸穿过半导体衬底和第一介电层形成。 第一和第二导电通孔通过第二电介质材料与半导体衬底隔离。 在第一电介质层上形成第一导电性的第一阳极/阴极层,并与第一导电通孔电耦合。 在第一阳极/阴极层上形成本征半导体层。 在本征半导体层上形成具有与第一导电性相反的第二导电性的第二阳极/阴极层,并与第二导电通孔电耦合。

    Front Lit PIN/NIP Diode Having a Continuous Anode/Cathode
    2.
    发明申请
    Front Lit PIN/NIP Diode Having a Continuous Anode/Cathode 有权
    具有连续阳极/阴极的前引脚PIN / NIP二极管

    公开(公告)号:US20070111356A1

    公开(公告)日:2007-05-17

    申请号:US11554437

    申请日:2006-10-30

    IPC分类号: H01L21/00 H01L29/82

    摘要: A photodetector includes a semiconductor substrate having first and second main surfaces opposite to each other. The photodetector includes at least one trench formed in the first main surface and a first anode/cathode region having a first conductivity formed proximate the first main surface and sidewalls of the at least one trench. The photodetector includes a second anode/cathode region proximate the second main surface. The second anode/cathode region has a second conductivity opposite the first conductivity. The at least one trench extends to the second main surface of the semiconductor substrate.

    摘要翻译: 光检测器包括具有彼此相对的第一和第二主表面的半导体衬底。 光电检测器包括形成在第一主表面中的至少一个沟槽和第一阳极/阴极区域,其具有靠近第一主表面和至少一个沟槽的侧壁附近形成的第一导电性。 光电检测器包括靠近第二主表面的第二阳极/阴极区域。 第二阳极/阴极区具有与第一导电性相反的第二导电性。 至少一个沟槽延伸到半导体衬底的第二主表面。

    Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes
    3.
    发明申请
    Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes 有权
    使用隔离扩散作为相邻光电二极管之间的串扰抑制剂的光电检测器阵列

    公开(公告)号:US20070085117A1

    公开(公告)日:2007-04-19

    申请号:US11548546

    申请日:2006-10-11

    IPC分类号: H01L31/113

    CPC分类号: H01L27/14683 H01L27/1463

    摘要: A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate.

    摘要翻译: 光电检测器阵列包括具有相对的第一和第二主表面的半导体衬底,靠近第一主表面的第一掺杂浓度的第一层和靠近第二主表面的第二掺杂浓度的第二层。 光电检测器包括形成在第一主表面中的至少一个导电通孔和靠近第一主表面和至少一个导电通孔的阳极/阴极区域。 通孔延伸到第二主表面。 导电通孔通过第一电介质材料与半导体衬底隔离。 阳极/阴极区域是与第一导电性相反的第二导电性。 光电检测器包括形成在第一主表面中并延伸穿过半导体衬底的第一层的至少第二层半导体衬底的第三掺杂浓度的掺杂隔离区。

    METHOD OF MANUFACTURING A PHOTODIODE ARRAY WITH THROUGH-WAFER VIAS
    4.
    发明申请
    METHOD OF MANUFACTURING A PHOTODIODE ARRAY WITH THROUGH-WAFER VIAS 有权
    使用透湿膜制作光电子阵列的方法

    公开(公告)号:US20080099870A1

    公开(公告)日:2008-05-01

    申请号:US11837150

    申请日:2007-08-10

    IPC分类号: H01L31/105 H01L31/18

    摘要: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main surface. A via is formed in the substrate which extends to a first depth position relative to the first main surface. The via has a first aspect ratio. Generally simultaneously with forming the via, an isolation trench is formed in the substrate spaced apart from the via which extends to a second depth position relative to the first main surface. The isolation trench has a second aspect ratio different from the first aspect ratio.

    摘要翻译: 一种制造光电二极管阵列的方法包括提供具有彼此相对的第一和第二主表面的半导体衬底。 半导体衬底具有靠近第一主表面的第一导电的第一层和靠近第二主表面的第二导电的第二层。 在衬底中形成通孔,该通孔相对于第一主表面延伸到第一深度位置。 通孔具有第一宽高比。 通常在形成通孔的同时,在与通孔间隔开的基板中形成隔离沟槽,其相对于第一主表面延伸到第二深度位置。 隔离沟槽具有与第一宽高比不同的第二宽高比。

    Technique for Stable Processing of Thin/Fragile Substrates

    公开(公告)号:US20070262378A1

    公开(公告)日:2007-11-15

    申请号:US11380457

    申请日:2006-04-27

    CPC分类号: H01L21/78

    摘要: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.

    FRONT SIDE ELECTRICAL CONTACT FOR PHOTODETECTOR ARRAY AND METHOD OF MAKING SAME
    6.
    发明申请
    FRONT SIDE ELECTRICAL CONTACT FOR PHOTODETECTOR ARRAY AND METHOD OF MAKING SAME 失效
    用于光电转换器阵列的前侧电触头及其制造方法

    公开(公告)号:US20070215968A1

    公开(公告)日:2007-09-20

    申请号:US11681543

    申请日:2007-03-02

    IPC分类号: H01L27/14

    CPC分类号: H01L27/1446 H01L31/022408

    摘要: A photodiode includes a semiconductor having front and backside surfaces and first and second active layers of opposite conductivity, separated by an intrinsic layer. A plurality of isolation trenches filled with conductive material extend into the first active layer, dividing the photodiode into a plurality of cells and forming a central trench region in electrical communication with the first active layer beneath each of the cells. Sidewall active diffusion regions extend the trench depth along each sidewall and are formed by doping at least a portion of the sidewalls with a dopant of first conductivity. A first contact electrically communicates with the first active layer beneath each of the cells via the central trench region. A plurality of second contacts each electrically communicate with the second active layer of one of the plurality of cells. The first and second contacts are formed on the front surface of the photodiode.

    摘要翻译: 光电二极管包括具有前后表面的半导体以及由本征层隔开的相反电导率的第一和第二有源层。 填充有导电材料的多个隔离沟槽延伸到第一有源层中,将光电二极管分成多个单元并形成与每个单元下面的第一有源层电连通的中心沟槽区。 侧壁有源扩散区域沿着每个侧壁延伸沟槽深度,并且通过用第一导电性的掺杂剂掺杂至少一部分侧壁而形成。 第一接触件经由中心沟槽区域与每个电池单元之下的第一有源层电连通。 多个第二触点分别与多个单元之一的第二活性层电连通。 第一和第二触点形成在光电二极管的前表面上。

    PHOTODIODE HAVING INCREASED PROPORTION OF LIGHT-SENSITIVE AREA TO LIGHT-INSENSITIVE AREA
    7.
    发明申请
    PHOTODIODE HAVING INCREASED PROPORTION OF LIGHT-SENSITIVE AREA TO LIGHT-INSENSITIVE AREA 有权
    光敏感区域增加光敏感区域的光敏面积

    公开(公告)号:US20070205478A1

    公开(公告)日:2007-09-06

    申请号:US11681576

    申请日:2007-03-02

    IPC分类号: H01L27/14

    摘要: A photodiode having an increased proportion of light-sensitive area to light-insensitive area includes a semiconductor having a backside surface and a light-sensitive frontside surface. The semiconductor includes a first active layer having a first conductivity, a second active layer having a second conductivity opposite the first conductivity, and an intrinsic layer separating the first and second active layers. A plurality of isolation trenches are arranged to divide the photodiode into a plurality of cells. Each cell has a total frontside area including a cell active frontside area sensitive to light and a cell inactive frontside area not sensitive to light. The cell active frontside area forms at least 95 percent of the cell total frontside area. A method of forming the photodiode is also disclosed.

    摘要翻译: 光敏面积比例增加到光不敏感区域的光电二极管包括具有背面和感光前侧表面的半导体。 半导体包括具有第一导电性的第一有源层,具有与第一导电性相反的第二导电性的第二有源层和分离第一和第二有源层的本征层。 布置多个隔离沟以将光电二极管分成多个单元。 每个细胞具有包括对光敏感的细胞活性前方区域和对光不敏感的细胞非活动的前侧区域的总前方区域。 细胞活动前方区域形成至少95%的细胞总前方区域。 还公开了一种形成光电二极管的方法。

    Positive-Intrinsic-Negative (PIN) / Negative-Intrinsic-Positive (NIP) Diode
    8.
    发明申请
    Positive-Intrinsic-Negative (PIN) / Negative-Intrinsic-Positive (NIP) Diode 有权
    正 - 内 - 负(PIN)/负 - 本征 - 正(NIP)二极管

    公开(公告)号:US20070077725A1

    公开(公告)日:2007-04-05

    申请号:US11463613

    申请日:2006-08-10

    IPC分类号: H01L21/76

    摘要: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity.

    摘要翻译: 正 - 内 - 负(PIN)/负 - 本征 - 正(NIP)二极管包括具有彼此相对的第一和第二主表面的半导体衬底。 半导体衬底具有第一导电性。 PIN / NIP二极管包括形成在第一主表面中的至少一个沟槽,其限定至少一个台面。 沟槽延伸到半导体衬底中的第一深度位置。 PIN / NIP二极管包括靠近第一主表面和沟槽的侧壁和底部的第一阳极/阴极层。 第一阳极/阴极层具有与第一导电性相反的第二导电性。 PIN / NIP二极管包括靠近第二主表面的第二阳极/阴极层,衬在沟槽上的第一钝化材料和衬在台面上的第二钝化材料。 第二阳极/阴极层是第一导电性。

    Bonded-wafer Superjunction Semiconductor Device
    9.
    发明申请
    Bonded-wafer Superjunction Semiconductor Device 有权
    接合晶片超级结半导体器件

    公开(公告)号:US20070063217A1

    公开(公告)日:2007-03-22

    申请号:US11466132

    申请日:2006-08-22

    IPC分类号: H01L29/74

    摘要: A bonded-wafer semiconductor device includes a semiconductor substrate, a buried oxide layer disposed on a first main surface of the semiconductor substrate and a multi-layer device stack. The multi-layer device stack includes a first device layer of a first conductivity disposed on the buried oxide layer, a second device layer of a second conductivity disposed on the first device layer, a third device layer of the first conductivity disposed on the second device layer and a fourth device layer of the second conductivity disposed on the third device layer. A trench is formed in the multi-layer device stack. A mesa is defined by the trench. The mesa has first and second sidewalls. A first anode/cathode layer is disposed on a first sidewall of the multi-layer device stack, and a second anode/cathode layer is disposed on the second sidewall of the multi-layer device stack.

    摘要翻译: 接合晶片半导体器件包括半导体衬底,设置在半导体衬底的第一主表面上的掩埋氧化物层和多层器件堆叠。 多层器件堆叠包括设置在掩埋氧化物层上的第一导电体的第一器件层,设置在第一器件层上的第二导电体的第二器件层,设置在第二器件上的第一导电体的第三器件层 层和设置在第三器件层上的第二导电体的第四器件层。 在多层器件堆叠中形成沟槽。 台面由沟槽定义。 台面具有第一和第二侧壁。 第一阳极/阴极层设置在多层器件堆叠的第一侧壁上,第二阳极/阴极层设置在多层器件堆叠的第二侧壁上。

    Silicon Wafer Having Through-Wafer Vias
    10.
    发明申请
    Silicon Wafer Having Through-Wafer Vias 有权
    具有透过晶片通孔的硅晶片

    公开(公告)号:US20060275946A1

    公开(公告)日:2006-12-07

    申请号:US11381605

    申请日:2006-05-04

    IPC分类号: H01L21/00 H01L31/00

    摘要: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. A trench is formed in the semiconductor substrate at the first main surface. The trench extends to a first depth position in the semiconductor substrate. The trench is lined with the dielectric material. The trench is filled with a conductive material. An electrical component is electrically connected to the conductive material exposed at the first main surface. A cap is mounted to the first main surface. The cap encloses the electrical component and the electrical connection.

    摘要翻译: 一种制造半导体器件的方法包括提供具有彼此相对的第一和第二主表面的半导体衬底。 在第一主表面上的半导体衬底中形成沟槽。 沟槽延伸到半导体衬底中的第一深度位置。 沟槽衬有介电材料。 沟槽填充有导电材料。 电气部件电连接到在第一主表面露出的导电材料。 盖子安装到第一主表面。 盖子包围电气部件和电气连接。