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6 条记录 (耗时 0.022 秒)

    Multiplexed codec for an ADSL system
    1.
    发明授权
    Multiplexed codec for an ADSL system 有权
    用于ADSL系统的多路复用编解码器

    公开(公告)号：US06459684B1

    公开(公告)日：2002-10-01

    申请号：US09250426

    申请日：1999-02-16

    申请人： Cormac S. Conroy ,  Samuel W. Sheng ,  Gregory T. Uehara

    发明人： Cormac S. Conroy ,  Samuel W. Sheng ,  Gregory T. Uehara

    IPC分类号： H04B320

    CPC分类号： H04L5/023

    摘要： An ADSL central office transmission system for transmitting downstream DMT signals to a plurality of remote ADSL transceiver is disclosed. The system includes a DMT digital signal transceiver that generates a time division multiplexed digital signal that includes a plurality of DMT signals to be sent on a plurality of ADSL lines. A digital to analog converter converts the time division multiplexed digital signal into a time division multiplexed analog signal that includes a plurality of analog DMT signals. The analog to digital converter has an output that outputs the time division multiplexed analog signal. A switch selectively connects the output of the digital to analog converter to each of a plurality of transmitters. The transmitters are configured to drive the plurality of ADSL lines. Thus, the plurality ADSL lines are driven by the plurality of analog DMT signals.

    摘要翻译： 公开了一种用于将下行DMT信号发送到多个远程ADSL收发器的ADSL中心局传输系统。 该系统包括DMT数字信号收发器，其产生包括要在多条ADSL线路上发送的多个DMT信号的时分复用数字信号。 数模转换器将时分多路复用数字信号转换成包括多个模拟DMT信号的时分复用模拟信号。 模数转换器具有输出时分复用的模拟信号的输出。 开关选择性地将数模转换器的输出连接到多个发射器中的每一个。 发射机被配置为驱动多条ADSL线路。 因此，多个ADSL线由多个模拟DMT信号驱动。

    False lock detection mechanism for use in a delay locked loop circuit
    2.
    发明授权
    False lock detection mechanism for use in a delay locked loop circuit 失效
    用于延迟锁定环路电路的假锁定检测机制

    公开(公告)号：US07733138B2

    公开(公告)日：2010-06-08

    申请号：US11226687

    申请日：2005-09-14

    申请人： Gregory T. Uehara ,  Ravikanth Suravarapu

    发明人： Gregory T. Uehara ,  Ravikanth Suravarapu

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/0891

    摘要： The delay locked loop circuit includes a charge pump circuit that may charge and discharge in response to an assertion of an up signal and a down signal, respectively. The delay locked loop circuit also includes a detection circuit that may assert the up signal indicating an occurrence of a transition of a first clock signal and may assert the down signal indicating an occurrence of a transition of a second clock signal. The delay locked loop circuit further includes a delay circuit that may provide a plurality of delayed clock signals and an additional delayed clock signal, each corresponding to a delayed version of the first clock signal. Further, a false lock circuit may provide a reset signal to the detection circuit dependent upon whether a predetermined number of successive clock edges associated with the delayed clock signals occur within a given clock cycle of the first clock signal.

    摘要翻译： 延迟锁定环电路包括电荷泵电路，其可以分别响应于上升信号和下降信号的断言而充电和放电。 延迟锁定环电路还包括检测电路，其可以断言指示第一时钟信号的转变的发生的上行信号，并且可以断言指示出现第二时钟信号的转变的向下信号。 延迟锁定环电路还包括延迟电路，其可以提供多个延迟的时钟信号和附加的延迟的时钟信号，每个对应于第一时钟信号的延迟版本。 此外，错误锁定电路可以根据在第一时钟信号的给定时钟周期内是否发生与延迟的时钟信号相关联的预定数量的连续时钟边沿，向检测电路提供复位信号。

    Spread-spectrum continous-time analog correlator and method therefor
    5.
    发明授权
    Spread-spectrum continous-time analog correlator and method therefor 失效
    扩频连续时间模拟相关器及其方法

    公开(公告)号：US06330274B1

    公开(公告)日：2001-12-11

    申请号：US09391117

    申请日：1999-09-07

    申请人： Gregory T. Uehara

    发明人： Gregory T. Uehara

    IPC分类号： H04B1707

    CPC分类号： H04B1/709 ,  H04B1/707 ,  H04B1/7075 ,  H04B1/7115

    摘要： The present invention is a correlator for use in spread spectrum applications which utilizing continuous-time analog domain signal processing. The correlator include a multiplier which is coupled to an integration capacitance, and an integration reset circuit which is coupled to the integration capacitance. The correlator is designed to receive a first input signal and a second input signal. The multiplier multiplies the first input signal and the second input signal to produce a multiplier output current. The multiplier output current is then integrated by the integration capacitance which produces a correlator output voltage. The integration reset circuit then reset the integration capacitance to a reset voltage.

    摘要翻译： 本发明是一种利用连续时间模拟域信号处理的扩展频谱应用中的相关器。 相关器包括耦合到积分电容的乘法器和耦合到积分电容的积分复位电路。 相关器被设计为接收第一输入信号和第二输入信号。 乘法器将第一输入信号和第二输入信号相乘以产生乘法器输出电流。 乘法器输出电流然后由产生相关器输出电压的积分电容积分。 然后，积分复位电路将积分电容复位为复位电压。

    Digitally calibrated bandgap reference
    6.
    发明授权
    Digitally calibrated bandgap reference 有权
    数字校准带隙参考

    公开(公告)号：US06275098B1

    公开(公告)日：2001-08-14

    申请号：US09411342

    申请日：1999-10-01

    申请人： Gregory T. Uehara ,  Samuel Sheng ,  Cormac Conroy

    发明人： Gregory T. Uehara ,  Samuel Sheng ,  Cormac Conroy

    IPC分类号： G05F316

    CPC分类号： G05F3/30

    摘要： A system and method for compensating for a voltage offset between an inverting input and a noninverting input of an op amp to provide a stable bandgap reference. The method including measuring the voltage offset between the inverting input and the noninverting input of the op amp and searching for a compensating current input to the op amp that compensates for the voltage offset. A programmable current source is set to output the compensating current to the op amp.

    摘要翻译： 一种用于补偿运算放大器的反相输入和同相输入之间的电压偏移的系统和方法，以提供稳定的带隙基准。 该方法包括测量运算放大器的反相输入和同相输入之间的电压偏移，并搜索补偿电压输入到运放的补偿电压偏移。 可编程电流源设置为将补偿电流输出到运算放大器。