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1.发明授权
公开(公告)号：US4723229A
公开(公告)日：1988-02-02
申请号：US825842
申请日：1986-02-04
IPC分类号： G11C11/44 , G11C8/00 , G11C8/12 , G11C11/418 , G11C11/40
CPC分类号： G11C8/12 , G11C11/418
摘要： The invention relates to a (static) memory which is divided into a number of memory blocks, memory cells being arranged in rows and columns in each memory block. A row in a memory block is activated via a selection gate whereto there are applied an inverted row selection signal (which is applied to all memory blocks) and a non-inverted and an inverted block selection signal (which is applied to all section gates in a memory block). The selection gate comprises a P-MOS transistor and two parallel-connected N-MOS transistors. The junction between the P-MOS and the N-MOS transistors constitutes the gate output (for activating a row of cells). The row selection signal is applied to the gate electrode of the PMOS transistor and of a first N-MOS transistor. The inverted block selection signal is applied to the gate electrode of the other N-MOS transistor and the block selection signal is applied to the main electrode of the P-MOS transistor.
摘要翻译： 本发明涉及一种（静态）存储器，其被分成多个存储器块，每个存储块中以行和列排列存储单元。 通过选择门激活存储器块中的一行，其中施加了反相行选择信号（其被应用于所有存储器块）和非反相和反相块选择信号（其被应用于 一个记忆块）。 选择栅极包括P-MOS晶体管和两个并联的N-MOS晶体管。 P-MOS和N-MOS晶体管之间的结点构成栅极输出（用于激活一行单元）。 行选择信号被施加到PMOS晶体管的栅电极和第一N-MOS晶体管。 反向块选择信号被施加到另一个N-MOS晶体管的栅电极，并且块选择信号被施加到P-MOS晶体管的主电极。
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公开(公告)号：US4862417A
公开(公告)日：1989-08-29
申请号：US126396
申请日：1987-11-30
申请人： Frans J. List , Cathal G. Phelan
发明人： Frans J. List , Cathal G. Phelan
CPC分类号： G11C29/84
摘要： A memory incorporates redundancy in the form of one or more redundant columns. An applied binary address is first distributed between predecoders which form a 1-out-of-2.sup.n code from n bits received. For each non-redundant column there is available a part of a main decoder, each part receiving a different combination of the bits supplied by the predecoders, thus selecting the column. For each redundant column there is provided a redundancy decoder. The latter decoder receives all bits supplied by the predecoders, each time via a series connection of a activatable gating element and a fuse element. Per predecoder the outputs of the series connections are combined in a wired logic function. Each wired logic function forms an input signal of the actual redundancy decoder. When a redundant column is to be addressed, all fuse elements but one of a group are opened and the gating elements are activated. A memory column to be replaced is then uncoupled by way of another fuse element.
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公开(公告)号：US08576603B2
公开(公告)日：2013-11-05
申请号：US11719397
申请日：2005-11-08
申请人： Rob Verhaar , Guido J. M. Dormans , Maurits Storms , Roger Cuppens , Frans J. List , Robert H. Beurze
发明人： Rob Verhaar , Guido J. M. Dormans , Maurits Storms , Roger Cuppens , Frans J. List , Robert H. Beurze
CPC分类号： H01L27/1122 , H01L27/112 , H01L27/11226 , H01L27/115
摘要： Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.
摘要翻译： 用于将第一半导体器件上的闪存单元转换为第二半导体器件中的ROM存储单元的方法，所述第一和第二半导体器件各自布置在半导体衬底上，并且每个包括相同的器件部分和相同的布线方案 将设备部分分别连接到闪存单元和ROM存储单元; 所述闪存单元由非易失性存储器技术制成并且包括存取晶体管和浮置晶体管，所述浮动晶体管包括浮置栅极和控制栅极; 所述ROM存储器单元是以基线技术制成并且包括单个栅极晶体管，该方法包括操作基线技术中使用的至少一个基线掩模的布局; 所述操作包括：将所述至少一个基准掩码的布局合并到所述闪存单元的布局，以及通过从所述至少一个基线掩码中消除所述闪存单元的布局而将所述闪存单元的布局转换为一个ROM存储器单元的布局 ，根据闪存单元的布局来布置浮动晶体管，并指定闪存单元的存取晶体管的布局作为ROM存储单元的单栅极晶体管的布局。
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公开(公告)号：US20090296447A1
公开(公告)日：2009-12-03
申请号：US11719397
申请日：2005-11-08
申请人： Rob Verhaar , Guido J. M. Dormans , Maurits Storms , Roger Cuppens , Frans J. List , Robert H. Beurze
发明人： Rob Verhaar , Guido J. M. Dormans , Maurits Storms , Roger Cuppens , Frans J. List , Robert H. Beurze
CPC分类号： H01L27/1122 , H01L27/112 , H01L27/11226 , H01L27/115
摘要： Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.
摘要翻译： 用于将第一半导体器件上的闪存单元转换为第二半导体器件中的ROM存储单元的方法，所述第一和第二半导体器件各自布置在半导体衬底上，并且每个包括相同的器件部分和相同的布线方案 将设备部分分别连接到闪存单元和ROM存储单元; 所述闪存单元由非易失性存储器技术制成并且包括存取晶体管和浮置晶体管，所述浮动晶体管包括浮置栅极和控制栅极; 所述ROM存储器单元是以基线技术制成并且包括单个栅极晶体管，该方法包括操作基线技术中使用的至少一个基线掩模的布局; 所述操作包括：将所述至少一个基准掩码的布局合并到所述闪存单元的布局，以及通过从所述至少一个基线掩码中消除所述闪存单元的布局而将所述闪存单元的布局转换为一个ROM存储器单元的布局 ，根据闪存单元的布局来布置浮动晶体管，并指定闪存单元的存取晶体管的布局作为ROM存储单元的单栅极晶体管的布局。
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