公开(公告)号：US08576603B2

公开(公告)日：2013-11-05

申请号：US11719397

申请日：2005-11-08

申请人： Rob Verhaar ,  Guido J. M. Dormans ,  Maurits Storms ,  Roger Cuppens ,  Frans J. List ,  Robert H. Beurze

发明人： Rob Verhaar ,  Guido J. M. Dormans ,  Maurits Storms ,  Roger Cuppens ,  Frans J. List ,  Robert H. Beurze

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C11/34

CPC分类号： H01L27/1122 ,  H01L27/112 ,  H01L27/11226 ,  H01L27/115

摘要： Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.

摘要翻译： 用于将第一半导体器件上的闪存单元转换为第二半导体器件中的ROM存储单元的方法，所述第一和第二半导体器件各自布置在半导体衬底上，并且每个包括相同的器件部分和相同的布线方案 将设备部分分别连接到闪存单元和ROM存储单元; 所述闪存单元由非易失性存储器技术制成并且包括存取晶体管和浮置晶体管，所述浮动晶体管包括浮置栅极和控制栅极; 所述ROM存储器单元是以基线技术制成并且包括单个栅极晶体管，该方法包括操作基线技术中使用的至少一个基线掩模的布局; 所述操作包括：将所述至少一个基准掩码的布局合并到所述闪存单元的布局，以及通过从所述至少一个基线掩码中消除所述闪存单元的布局而将所述闪存单元的布局转换为一个ROM存储器单元的布局 ，根据闪存单元的布局来布置浮动晶体管，并指定闪存单元的存取晶体管的布局作为ROM存储单元的单栅极晶体管的布局。

公开(公告)号：US5879990A

公开(公告)日：1999-03-09

申请号：US814868

申请日：1997-03-11

申请人： Guido J. M. Dormans ,  Robertus D. J. Verhaar ,  Roger Cuppens

发明人： Guido J. M. Dormans ,  Robertus D. J. Verhaar ,  Roger Cuppens

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/43 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/42324

摘要： The invention relates in particular, though not exclusively, to an integrated circuit with an embedded non-volatile memory with floating gate (10). According to the invention, at least two poly layers of equal or at least substantially equal thickness are used for this device. The first poly layer, poly A, is for the floating gate (10) and for the gates (22) of NMOS and PMOS in the logic portion of the circuit. The second poly layer, poly B, serves exclusively for the control electrode (21) above the floating gate. If so desired, a third poly layer may be deposited for both the control electrode and the logic gates, so that the thicknesses of these electrodes, and thus their resistances, are given desired values. Problems like overetching and bridging during saliciding are prevented in that the control electrode and the logic gates have the same thickness.

摘要翻译： 本发明特别涉及具有带有浮动栅极（10）的嵌入式非易失性存储器的集成电路（尽管并非排他地）。 根据本发明，对于该装置使用至少两个相等或至少基本相等厚度的多层。 第一多晶硅层poly是用于浮置栅极（10）和电路的逻辑部分中的NMOS和PMOS的栅极（22）。 第二多晶硅层poly B专门用于浮栅之上的控制电极（21）。 如果需要，可以为控制电极和逻辑门两者沉积第三多晶硅层，使得这些电极的厚度以及因此它们的电阻被赋予所需的值。 由于控制电极和逻辑门具有相同的厚度，所以防止了在浇注过程中过蚀刻和桥接的问题。

公开(公告)号：US06069033A

公开(公告)日：2000-05-30

申请号：US44544

申请日：1998-03-19

申请人： Robertus D. J. Verhaar ,  Guido J. M. Dormans

发明人： Robertus D. J. Verhaar ,  Guido J. M. Dormans

IPC分类号： H01L21/8238 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11526 ,  H01L21/8238 ,  H01L27/105 ,  H01L27/11546

摘要： The invention provides a method of combining an EPROM (or EEPROM) with a standard CMOS process. After growing the gate oxide 9, a lightly doped polycrystalline or amorphous silicon layer 10, hereinafter referred to as poly I, is deposited. In this layer, the floating gate 13 of the memory cells is defined, while, outside the memory matrix, the surface remains covered with poly I. Subsequently, the source/drain implantation in the memory cells is carried out. The poly layer 10 situated outside the memory matrix is masked against this heavy implantation by the mask 11. Subsequently, a second poly layer can be provided from which the control gates of the memory cells are formed and which forms a coherent layer with the existing poly I layer outside the matrix. In a subsequent series of steps in a standard CMOS process, the n-ch MOSTs and p-ch MOSTs are provided, n-type gates 22 for the n-ch MOSTs and p-type gates 23 for the p-ch MOSTs being formed from the poly I layer.

摘要翻译： 本发明提供了一种将EPROM（或EEPROM）与标准CMOS工艺组合的方法。 在生长栅极氧化物9之后，沉积轻掺杂多晶或非晶硅层10（以下称为聚I）。 在该层中，定义了存储单元的浮置栅极13，而在存储器矩阵之外，表面保持被多晶I覆盖。随后，执行存储单元中的源极/漏极注入。 位于存储器矩阵之外的多晶硅层10被掩模11遮蔽以防止这种重度注入。随后，可以提供第二多晶硅层，存储单元的控制栅极从该第二多晶硅层形成，并且与现有的聚 我层叠在矩阵之外。 在标准CMOS工艺中的随后的一系列步骤中，提供n沟道MOST和p沟道MOST，形成用于n沟道MOST的n型栅极22和用于p沟道MOST的p型栅极23 从多层I层。

公开(公告)号：US20090296447A1

公开(公告)日：2009-12-03

申请号：US11719397

申请日：2005-11-08

申请人： Rob Verhaar ,  Guido J. M. Dormans ,  Maurits Storms ,  Roger Cuppens ,  Frans J. List ,  Robert H. Beurze

发明人： Rob Verhaar ,  Guido J. M. Dormans ,  Maurits Storms ,  Roger Cuppens ,  Frans J. List ,  Robert H. Beurze

IPC分类号： G11C5/06 ,  H01L21/00 ,  H01L21/77 ,  G06F17/50

CPC分类号： H01L27/1122 ,  H01L27/112 ,  H01L27/11226 ,  H01L27/115

摘要： Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.

摘要翻译： 用于将第一半导体器件上的闪存单元转换为第二半导体器件中的ROM存储单元的方法，所述第一和第二半导体器件各自布置在半导体衬底上，并且每个包括相同的器件部分和相同的布线方案 将设备部分分别连接到闪存单元和ROM存储单元; 所述闪存单元由非易失性存储器技术制成并且包括存取晶体管和浮置晶体管，所述浮动晶体管包括浮置栅极和控制栅极; 所述ROM存储器单元是以基线技术制成并且包括单个栅极晶体管，该方法包括操作基线技术中使用的至少一个基线掩模的布局; 所述操作包括：将所述至少一个基准掩码的布局合并到所述闪存单元的布局，以及通过从所述至少一个基线掩码中消除所述闪存单元的布局而将所述闪存单元的布局转换为一个ROM存储器单元的布局 ，根据闪存单元的布局来布置浮动晶体管，并指定闪存单元的存取晶体管的布局作为ROM存储单元的单栅极晶体管的布局。

公开(公告)号：US06326661B1

公开(公告)日：2001-12-04

申请号：US09616630

申请日：2000-07-26

申请人： Guido J. M. Dormans ,  Robertus D. J. Verhaar

发明人： Guido J. M. Dormans ,  Robertus D. J. Verhaar

IPC分类号： H01L29788

CPC分类号： H01L27/115 ,  H01L29/42328

摘要： A semiconductor device comprises a semiconductor body (1) having a region (2) of a first conductivity type adjoining a surface (3) of the semiconductor body (1), which semiconductor body (1) is provided at the surface (3) with a non-volatile memory cell. The memory cell comprises a source (4) and a drain (5) of an opposite, second conductivity type provided in the semiconductor body (1), between which source (4) and drain (5) the surface (3) of the semiconductor body (1) is provided with a floating gate (6) and a select gate (10). The floating gate (6) and the select gate (10) both have a substantially flat surface portion (13) extending substantially parallel to the surface (3) of the semiconductor body (1) and side-wall portions (14) extending substantially transversely to the surface (3) of the semiconductor body (1). A control gate (7) is situated above the floating gate (6), and is capacitively coupled to the substantially flat surface portion (13) of the floating gate (6) and to at least the side-wall portions (14) of the floating gate (6) facing the source (4) and the drain (5). Moreover, the control gate (7) overlaps the select gate (10) and ends above the substantially flat surface portion (13) of the select gate (10).

摘要翻译： 一种半导体器件包括具有邻接半导体本体（1）的表面（3）的第一导电类型的区域（2）的半导体本体（1），该半导体本体（1）设置在表面（3）处， 非易失性存储单元。 存储单元包括设置在半导体本体（1）中的相对的第二导电类型的源极（4）和漏极（5），源极（4）和漏极（5）之间的半导体器件的表面（3） 主体（1）设置有浮动门（6）和选择门（10）。 浮动栅极（6）和选择栅极（10）都具有基本上平行于半导体本体（1）的表面（3）延伸的基本平坦的表面部分（13），并且基本横向延伸的侧壁部分 到半导体本体（1）的表面（3）。 控制栅极（7）位于浮动栅极（6）的上方，并且电容耦合到浮动栅极（6）的基本上平坦的表面部分（13）并且至少连接到浮动栅极（6）的侧壁部分（14） 浮动栅极（6）面向源极（4）和漏极（5）。 此外，控制栅极（7）与选择栅极（10）重叠并且结束在选择栅极（10）的基本上平坦的表面部分（13）之上。

公开(公告)号：US06174759B1

公开(公告)日：2001-01-16

申请号：US09304412

申请日：1999-05-03

申请人： Robertus D. J. Verhaar ,  Joachim C. H. Garbe ,  Guido J. M. Dormans

发明人： Robertus D. J. Verhaar ,  Joachim C. H. Garbe ,  Guido J. M. Dormans

IPC分类号： H01L218234

CPC分类号： H01L27/11526 ,  H01L27/11546

摘要： In the manufacture of integrated circuits with an embedded non-volatile memory, it is known to first provide the greater part of the memory and subsequently provide the CMOS logic in a second series of steps of a standard CMOS process. By virtue of this separation of process steps, it is possible to optimize the non-volatile memory substantially without degrading the logic. According to the invention, this process is further optimized in that, particularly for the periphery of the memory, and simultaneously with the memory transistors (21, 24, 27), transistors are manufactured which can cope with a higher voltage than the transistors of the logic. In the case of an EEPROM, each cell of the memory is provided with such a high-voltage transistor as a selection transistor (22, 24). Apart from the n-well implantation (5), high-voltage transistors of the p-channel are largely manufactured by means of the same process steps as the p-channel transistors in the logic, so that the number of process steps remains limited. By adding a single mask, the circuit may also be provided with a Flash or an OTP (One Time Programmable) memory.

摘要翻译： 在具有嵌入式非易失性存储器的集成电路的制造中，已知首先提供大部分存储器，并随后在标准CMOS工艺的第二系列步骤中提供CMOS逻辑。 由于处理步骤的这种分离，可以基本上不劣化逻辑来优化非易失性存储器。 根据本发明，该方法进一步优化，特别是对于存储器的周边，并且与存储晶体管（21,24,27）同时地，制造了能够处理比该晶体管的晶体管更高的电压的晶体管 逻辑。 在EEPROM的情况下，存储器的每个单元设置有作为选择晶体管（22,24）的这种高压晶体管。 除了n阱注入（5）之外，p沟道的高电压晶体管通过与逻辑中的p沟道晶体管相同的工艺步骤大量制造，使得工艺步骤的数量仍然有限。 通过添加单个掩模，电路还可以设置有闪存或OTP（一次可编程）存储器。