公开(公告)号：US08576603B2

公开(公告)日：2013-11-05

申请号：US11719397

申请日：2005-11-08

申请人： Rob Verhaar ,  Guido J. M. Dormans ,  Maurits Storms ,  Roger Cuppens ,  Frans J. List ,  Robert H. Beurze

发明人： Rob Verhaar ,  Guido J. M. Dormans ,  Maurits Storms ,  Roger Cuppens ,  Frans J. List ,  Robert H. Beurze

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C11/34

CPC分类号： H01L27/1122 ,  H01L27/112 ,  H01L27/11226 ,  H01L27/115

摘要： Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.

摘要翻译： 用于将第一半导体器件上的闪存单元转换为第二半导体器件中的ROM存储单元的方法，所述第一和第二半导体器件各自布置在半导体衬底上，并且每个包括相同的器件部分和相同的布线方案 将设备部分分别连接到闪存单元和ROM存储单元; 所述闪存单元由非易失性存储器技术制成并且包括存取晶体管和浮置晶体管，所述浮动晶体管包括浮置栅极和控制栅极; 所述ROM存储器单元是以基线技术制成并且包括单个栅极晶体管，该方法包括操作基线技术中使用的至少一个基线掩模的布局; 所述操作包括：将所述至少一个基准掩码的布局合并到所述闪存单元的布局，以及通过从所述至少一个基线掩码中消除所述闪存单元的布局而将所述闪存单元的布局转换为一个ROM存储器单元的布局 ，根据闪存单元的布局来布置浮动晶体管，并指定闪存单元的存取晶体管的布局作为ROM存储单元的单栅极晶体管的布局。

公开(公告)号：US20090296447A1

公开(公告)日：2009-12-03

申请号：US11719397

申请日：2005-11-08

申请人： Rob Verhaar ,  Guido J. M. Dormans ,  Maurits Storms ,  Roger Cuppens ,  Frans J. List ,  Robert H. Beurze

发明人： Rob Verhaar ,  Guido J. M. Dormans ,  Maurits Storms ,  Roger Cuppens ,  Frans J. List ,  Robert H. Beurze

IPC分类号： G11C5/06 ,  H01L21/00 ,  H01L21/77 ,  G06F17/50

CPC分类号： H01L27/1122 ,  H01L27/112 ,  H01L27/11226 ,  H01L27/115

摘要： Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.

摘要翻译： 用于将第一半导体器件上的闪存单元转换为第二半导体器件中的ROM存储单元的方法，所述第一和第二半导体器件各自布置在半导体衬底上，并且每个包括相同的器件部分和相同的布线方案 将设备部分分别连接到闪存单元和ROM存储单元; 所述闪存单元由非易失性存储器技术制成并且包括存取晶体管和浮置晶体管，所述浮动晶体管包括浮置栅极和控制栅极; 所述ROM存储器单元是以基线技术制成并且包括单个栅极晶体管，该方法包括操作基线技术中使用的至少一个基线掩模的布局; 所述操作包括：将所述至少一个基准掩码的布局合并到所述闪存单元的布局，以及通过从所述至少一个基线掩码中消除所述闪存单元的布局而将所述闪存单元的布局转换为一个ROM存储器单元的布局 ，根据闪存单元的布局来布置浮动晶体管，并指定闪存单元的存取晶体管的布局作为ROM存储单元的单栅极晶体管的布局。

公开(公告)号：US5879990A

公开(公告)日：1999-03-09

申请号：US814868

申请日：1997-03-11

申请人： Guido J. M. Dormans ,  Robertus D. J. Verhaar ,  Roger Cuppens

发明人： Guido J. M. Dormans ,  Robertus D. J. Verhaar ,  Roger Cuppens

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/43 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/42324

摘要： The invention relates in particular, though not exclusively, to an integrated circuit with an embedded non-volatile memory with floating gate (10). According to the invention, at least two poly layers of equal or at least substantially equal thickness are used for this device. The first poly layer, poly A, is for the floating gate (10) and for the gates (22) of NMOS and PMOS in the logic portion of the circuit. The second poly layer, poly B, serves exclusively for the control electrode (21) above the floating gate. If so desired, a third poly layer may be deposited for both the control electrode and the logic gates, so that the thicknesses of these electrodes, and thus their resistances, are given desired values. Problems like overetching and bridging during saliciding are prevented in that the control electrode and the logic gates have the same thickness.

摘要翻译： 本发明特别涉及具有带有浮动栅极（10）的嵌入式非易失性存储器的集成电路（尽管并非排他地）。 根据本发明，对于该装置使用至少两个相等或至少基本相等厚度的多层。 第一多晶硅层poly是用于浮置栅极（10）和电路的逻辑部分中的NMOS和PMOS的栅极（22）。 第二多晶硅层poly B专门用于浮栅之上的控制电极（21）。 如果需要，可以为控制电极和逻辑门两者沉积第三多晶硅层，使得这些电极的厚度以及因此它们的电阻被赋予所需的值。 由于控制电极和逻辑门具有相同的厚度，所以防止了在浇注过程中过蚀刻和桥接的问题。

公开(公告)号：US20060056223A1

公开(公告)日：2006-03-16

申请号：US10515475

申请日：2003-05-19

申请人： Anthonie Ditewig ,  Roger Cuppens

发明人： Anthonie Ditewig ,  Roger Cuppens

IPC分类号： G11C11/22

CPC分类号： G11C11/16 ,  G11C11/15

摘要： An MRAM memory is proposed which gives a maximum read-out signal. This is advantageous for high-speed sensing of the MRAM bits. In an MRAM memory with magnetoresistive memory cells linked together to form logically organized rows and columns, It is obtained by, at least during writing, connecting write bitlines of two adjacent rows or columns with each other, so as to write inverse data values in two adjacent memory cells. In this way, a return path for the writing current is provided in a small loop, which enhances EMC behavior.

摘要翻译： 提出了一种提供最大读出信号的MRAM存储器。 这对于MRAM位的高速感测是有利的。 在具有连接在一起形成逻辑组织的行和列的磁阻存储器单元的MRAM存储器中，至少在写入期间通过将两个相邻行或列的写位线彼此连接来获得，以便将二进制数据值写入二 相邻的存储单元。 以这种方式，写入电流的返回路径以小环路提供，这增强了EMC行为。

公开(公告)号：US4862418A

公开(公告)日：1989-08-29

申请号：US266346

申请日：1988-11-01

申请人： Roger Cuppens ,  Joannes J. M. Koomen

发明人： Roger Cuppens ,  Joannes J. M. Koomen

IPC分类号： H01L27/10 ,  G11C16/04 ,  G11C17/00 ,  G11C29/00 ,  G11C29/24

CPC分类号： G11C29/24

摘要： In programmable memories of the EPROM or EEPROM type, a row and/or column of test memory cells are added to the matrix of rows and columns of non-volatile memory cells for the testing of the peripheral circuits which select and read the memory cells. The test memory cells have a very short write time as compared with the non-volatile memory cells and may be of the dynamic (or volatile) type. The write time for a memory cell of the EPROM or EEPROM may be, for example, 10 msec. The write time for a dynamic memory cell, however, is 100 nsec. The time required for testing the peripheral circuits can therefore be reduced by a factor of 80 (for a 16 Kbit memory) or higher (for memories larger than 16 Kbits).

摘要翻译： 在EPROM或EEPROM类型的可编程存储器中，测试存储器单元的行和/或列被添加到非易失性存储单元的行和列的矩阵中，用于测试选择和读取存储单元的外围电路。 测试存储单元与非易失性存储单元相比具有非常短的写入时间，并且可以是动态（或易失性）类型。 EPROM或EEPROM的存储单元的写入时间可以是例如10毫秒。 然而，动态存储单元的写入时间为100ns。 因此，测试外围电路所需的时间可以降低80倍（对于16 Kbit存储器）或更高（对于大于16 Kbits的存储器）。

公开(公告)号：US4616339A

公开(公告)日：1986-10-07

申请号：US618006

申请日：1984-06-06

申请人： Roger Cuppens ,  Cornelis D. Hartgring

发明人： Roger Cuppens ,  Cornelis D. Hartgring

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C7/00

CPC分类号： G11C16/12

摘要： Field effect transistors having a short channel length are desirable for carrying out logic operations at a high speed. However, they are then not capable of withstanding the comparatively high programming and erasing voltage at which an (E)EPROM has to be operated. During the programming cycle the field effect transistors are kept in the current-nonconducting state, while recording the logic information obtained by the logic operations, the "fast" transistors are nevertheless capable of withstanding the comparatively high voltage.

摘要翻译： 具有短信道长度的场效应晶体管对于高速执行逻辑运算是理想的。 然而，它们不能承受必须操作（E）EPROM的相对较高的编程和擦除电压。 在编程周期期间，场效应晶体管保持在电流 - 非导通状态，同时记录通过逻辑运算获得的逻辑信息，但是“快速”晶体管仍能承受较高的电压。

公开(公告)号：US07986548B2

公开(公告)日：2011-07-26

申请号：US10536271

申请日：2003-10-29

申请人： Anthonie Meindert Herman Ditewig ,  Roger Cuppens

发明人： Anthonie Meindert Herman Ditewig ,  Roger Cuppens

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： The present invention provides a method and device for programming a magnetic random access memory element with reduced current consumption, by re-routing digitline current through a selected bitline in a selected direction.

摘要翻译： 本发明提供一种用于通过在所选方向上重新路由选定位线的数字线电流来编程具有降低的电流消耗的磁随机存取存储器元件的方法和装置。

公开(公告)号：US20060062067A1

公开(公告)日：2006-03-23

申请号：US10515155

申请日：2003-05-16

申请人： Anthonie Ditewig ,  Roger Cuppens

发明人： Anthonie Ditewig ,  Roger Cuppens

IPC分类号： G11C7/00

CPC分类号： G11C11/16 ,  G11C8/16

摘要： The present invention describes a matrix with magnetoresistive memory cells arranged in logically organized rows and columns, Each memory cell includes a magnetoresistive element. The matrix comprises means for simultaneously reading from one cell in a column and writing to another cell in a column, or means for simultaneous reading from one cell in a row and writing to another cell in the same row. Such matrix can be used in a read-while-write MRAM memory.

摘要翻译： 本发明描述了一种具有按逻辑组织的行和列布置的磁阻存储器单元的矩阵。每个存储单元包括磁阻元件。 矩阵包括用于同时从列中的一个单元读取并写入列中的另一个单元的装置，或用于同时从一行中的一个单元读取并写入同一行中的另一单元的装置。 这样的矩阵可以用在读写MRAM存储器中。

公开(公告)号：US5895950A

公开(公告)日：1999-04-20

申请号：US838247

申请日：1997-04-17

申请人： Andrew J. Walker ,  Roger Cuppens ,  Alwin N. Kronert

发明人： Andrew J. Walker ,  Roger Cuppens ,  Alwin N. Kronert

IPC分类号： H01L21/8247 ,  G11C16/16 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7885 ,  G11C16/16 ,  H01L27/105 ,  H01L27/11526

摘要： The invention relates to a non-volatile memory with floating gate, in particular a Flash-EPROM, in which writing takes place through injection of hot electrons into the floating gate and in which erasing takes place through injection of hot holes. To keep the write and erase voltages sufficiently low, p-type zones which locally increase the background doping concentration of the p-type substrate are provided around the n-type source and drain zones. These p-type zones cause an increased field strength at the drain zone whereby hot electrons are formed at the pinch-off point also at lower voltages. This increased background concentration in addition reduces the breakdown voltage of the pn junction of the source and drain zones, so that hot holes for erasing can be formed by pn breakdown at comparatively low voltages. The device is particularly suitable for being integrated into a signal processing IC manufactured in a standard process, such as a microcontroller.

摘要翻译： 本发明涉及一种具有浮动栅极，特别是闪存EPROM的非易失性存储器，其中通过将热电子注入到浮动栅极中进行写入，并且其中通过注入热孔进行擦除。 为了保持写入和擦除电压足够低，在n型源极和漏极区域周围设置有局部增加p型衬底的背景掺杂浓度的p型区域。 这些p型区域在漏极区域引起增加的场强，从而也在较低电压下在夹断点处形成热电子。 此外，这种增加的背景浓度还降低了源区和漏区的pn结的击穿电压，从而可以通过在较低电压下的pn击穿来形成用于擦除的热孔。 该器件特别适合于集成到诸如微控制器的标准处理中制造的信号处理IC中。

公开(公告)号：US5216269A

公开(公告)日：1993-06-01

申请号：US745992

申请日：1991-08-08

申请人： Jan Middelhoek ,  Gerrit-Jan Hemink ,  Rutger C. M. Wijburg ,  Louis Praamsma ,  Roger Cuppens

发明人： Jan Middelhoek ,  Gerrit-Jan Hemink ,  Rutger C. M. Wijburg ,  Louis Praamsma ,  Roger Cuppens

IPC分类号： H01L29/788

CPC分类号： H01L29/7884

摘要： Each memory cell of an electrically-programmable semiconductor memory has a field-effect transistor with a charge-storage region. Efficient and fast injection of hot carriers into the charge-storage region is achieved by vertical punch-through of a depletion layer to a buried injector region, by application of programming voltages to a control gate and to the surface of the punch-through region. Non-injected carriers are removed via at least the transistor drain during the programming. A well-defined punch-through region can be obtained with a higher-doped boundary region at at least one side of the punch-through region to restrict the lateral spread of the depletion layer(s) and prevent parasitic connections. This permits closer spacing of the injector region to other regions of the memory cell, e.g. source and drain regions, and the injector region may adjoin an inset insulating field pattern. A compact cell array layout can be formed with a common connection region for the injector regions of two adjacent cells and for either a source or drain region of four other adjacent cells. The control gate and an erase gate may both be coupled in the same manner to the charge-storage region, and the cell can be operated with complementary voltage levels for writing and erasing. A feed-back mechanism with the start of injection from the punch-through and injector regions can provide a well-defined charge level limit for the erasure.

摘要翻译： 电可编程半导体存储器的每个存储单元具有具有电荷存储区域的场效应晶体管。 通过将编程电压施加到控制栅极和穿通区域的表面，通过将耗尽层垂直穿透到埋入式注入器区域来实现热载流子进入电荷存储区域的高效和快速注入。 在编程期间，非注入载流子至少通过晶体管漏极去除。 可以在穿通区域的至少一侧具有较高掺杂的边界区域来获得明确的穿通区域，以限制耗尽层的横向扩展并防止寄生连接。 这允许注射器区域与存储器单元的其它区域的更近的间隔，例如， 源极和漏极区域，并且注入器区域可以邻接插入绝缘场图案。 紧凑的单元阵列布局可以形成有用于两个相邻单元的注入器区域和四个其它相邻单元的源极或漏极区域的公共连接区域。 控制栅极和擦除栅极都可以以相同的方式耦合到电荷存储区域，并且可以以互补的电压电平对单元进行操作以进行写入和擦除。 具有从穿通和注射器区域的注入开始的反馈机构可以为擦除提供明确定义的电荷水平限制。