公开(公告)号：US11495898B2

公开(公告)日：2022-11-08

申请号：US17146350

申请日：2021-01-11

Applicant: Credo Technology Group Limited

Inventor： Xike Liu ,  Zhining Li ,  Xiangxiang Ye ,  Gaige Mei

IPC: H01R3/00 ,  H01R12/53 ,  H05K1/11 ,  H01R43/02

Abstract: Connector paddle cards are provided with an improved wiring connection geometry that reduces impedance mismatch. One illustrative embodiment is a printed circuit board having, on at least one surface: edge connector traces arranged along a first edge for contacting electrical conductors in a socket connector; an outer set of electrodes arranged parallel to a second edge for attaching exposed ends of sheathed wires in a cable (“outer wires”); and an inner set of electrodes arranged parallel to the second edge for attaching exposed ends of sheathed wires in a cable (“inner wires”), with the electrodes in the inner set being staggered relative to the electrodes in the outer set.

公开(公告)号：US11756905B2

公开(公告)日：2023-09-12

申请号：US17194390

申请日：2021-03-08

Applicant: Credo Technology Group Limited

Inventor： Mengying Ma ,  Xike Liu ,  Xiangxiang Ye ,  Xin Wang

IPC: H01L23/66 ,  H03H11/28 ,  H03M9/00 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/49838 ,  H01L24/81 ,  H03H11/28 ,  H03M9/00 ,  H01L2223/6616 ,  H01L2224/81908 ,  H01L2224/81986 ,  H01L2924/30105 ,  H01L2924/30111

Abstract: An illustrative embodiment of a packaged integrated circuit includes: an integrated circuit chip having a SerDes signal pad; and a package substrate having a core via and an arrangement of micro-vias connecting the SerDes signal pad to an external contact for solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro-vias provides a pi-network inductance that improves connection impedance matching. An illustrative method embodiment includes: obtaining an expected impedance of the PCB trace; determining parasitic capacitances of a core via and a solder ball connection to the PCB trace; minimizing the core via capacitance; calculating a pi-network inductance that improves impedance matching with the PCB trace; and adjusting a micro-via arrangement between the core via and the solder ball connection to provide the pi-network inductance.