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公开(公告)号：US08890729B2
公开(公告)日：2014-11-18
申请号：US13751062
申请日：2013-01-26
发明人： Donald E. Lewis , Ryan James Kier , Rex K. Hales , Yusuf A. Haque
CPC分类号： H03M1/0673 , H03M1/1215 , H03M1/168
摘要： A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.
摘要翻译： 时间交织模数转换器（ADC）包括多个ADC; 定时发生器，其为所述多个ADC中的每一个产生停靠信号，使得所述时钟信号的边沿触发所述多个ADC对输入信号的采样; 以及定时调整电路，用于在由ADC接收对接信号之前接收和调整停靠信号，使得所述输入信号的采样在时间上间隔并以所需采样速率的1 / N倍的速率发生; 和随机数发生器，伪随机选择哪个ADC采样输入信号; 以及用于调整多个ADC的带宽的电路。
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公开(公告)号：US20140152478A1
公开(公告)日：2014-06-05
申请号：US13751062
申请日：2013-01-26
发明人： Donald E. Lewis , Ryan James Kier , Rex K. Hales , Yusuf A. Haque
IPC分类号： H03M1/12
CPC分类号： H03M1/0673 , H03M1/1215 , H03M1/168
摘要： A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.
摘要翻译： 时间交织模数转换器（ADC）包括多个ADC; 定时发生器，其为所述多个ADC中的每一个产生停靠信号，使得所述时钟信号的边沿触发所述多个ADC对输入信号的采样; 以及定时调整电路，用于在由ADC接收对接信号之前接收和调整停靠信号，使得所述输入信号的采样在时间上间隔并以所需采样速率的1 / N倍的速率发生; 和随机数发生器，伪随机选择哪个ADC采样输入信号; 以及用于调整多个ADC的带宽的电路。
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公开(公告)号：US20140152477A1
公开(公告)日：2014-06-05
申请号：US13706035
申请日：2012-12-05
发明人： Donald E. Lewis , Ryan James Kier , Rex K. Hales , Yusuf Haque
CPC分类号： H03M1/1061 , H03M1/1245 , H03M1/164
摘要： A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.
摘要翻译： 时间交织模数转换器（ADC）包括多个ADC; 定时发生器，用于为每个ADC产生时钟信号，使得所述时钟信号的边沿触发ADC的输入信号的采样; 以及定时调整电路，用于在由ADC接收时钟信号之前接收和调整时钟信号，使得所述输入信号的采样在时间上间隔并以所需采样速率的1 / N倍的速率发生; 以及用于调整多个ADC的带宽的电路。
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公开(公告)号：US08890739B2
公开(公告)日：2014-11-18
申请号：US13706035
申请日：2012-12-05
发明人： Donald E. Lewis , Ryan James Kier , Rex K. Hales , Yusuf Haque
CPC分类号： H03M1/1061 , H03M1/1245 , H03M1/164
摘要： A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.
摘要翻译： 时间交织模数转换器（ADC）包括多个ADC; 定时发生器，用于为每个ADC产生时钟信号，使得所述时钟信号的边沿触发ADC的输入信号的采样; 以及定时调整电路，用于在由ADC接收时钟信号之前接收和调整时钟信号，使得所述输入信号的采样在时间上间隔并以所需采样速率的1 / N倍的速率发生; 以及用于调整多个ADC的带宽的电路。
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