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    Providing a baseline capacitance for a capacitance sensing channel
    1.
    发明授权
    Providing a baseline capacitance for a capacitance sensing channel 有权

    公开(公告)号：US11481066B2

    公开(公告)日：2022-10-25

    申请号：US17363954

    申请日：2021-06-30

    Applicant: Cypress Semiconductor Corporation

    Inventor： Denis Ellis ,  Kaveh Hosseini ,  Timothy Williams ,  Gabriel Rowe ,  Roman Ogirko ,  Brendan Lawton

    IPC: G06F3/041 ,  G06F3/044

    Abstract: A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner generates a baseline current based on a time constant of the channel input associated with the measuring of the capacitance of the element of the capacitive sense array using the programmable baseline resistor. The capacitive hardware baseliner provides the baseline current at the channel input to provide a charge for a sense capacitor. A change in the charge of the sense capacitor is provided by the baseline current indicating a presence of a tough object proximate to the element.

    Over-voltage tolerant circuit and method
    6.
    发明授权
    Over-voltage tolerant circuit and method 有权
    过电压电路及方法

    公开(公告)号：US08902554B1

    公开(公告)日：2014-12-02

    申请号：US14037023

    申请日：2013-09-25

    Applicant: Cypress Semiconductor Corporation

    Inventor： Supreet Bhanja Deo ,  Timothy Williams ,  Pat Madden

    IPC: H02H3/20 ,  H03K17/08

    CPC classification number: H03K17/08122 ,  H03K2217/0063

    Abstract: Over-voltage tolerant circuits and methods are provided. In one embodiment, the circuit includes a pull-up transistor coupled to an I/O pad, a sensing circuit coupled to the I/O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad), a latch coupled to the sensing circuit to retain an output of the sensing circuit, and a selection circuit coupled to the sensing circuit through the latch. The selection circuit includes a first bias circuit to apply Vcc to a well and gate of the pull-up transistor, a second bias circuit to apply Vpad to the gate and the well of the pull-up transistor, and a non-overlap circuit configured to ensure the gate and the well of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of the sensing circuit.

    Abstract translation: 提供过电压容限电路和方法。 在一个实施例中，电路包括耦合到I / O焊盘的上拉晶体管，耦合到I / O焊盘和感测电压（Vcc）的感测电路，感测电路被配置为感测施加到I / 焊盘（Vpad），耦合到感测电路以保持感测电路的输出的锁存器，以及通过锁存器耦合到感测电路的选择电路。 所述选择电路包括：第一偏置电路，用于将Vcc施加到所述上拉晶体管的阱和栅极;第二偏置电路，用于将Vpad施加到所述上拉晶体管的栅极和阱;以及非重叠电路配置 以确保上拉晶体管的栅极和阱基本上总是由第一或第二偏置电路驱动，这取决于感测电路的输出。

    PROVIDING A BASELINE CAPACITANCE FOR A CAPACITANCE SENSING CHANNEL
    8.
    发明申请
    PROVIDING A BASELINE CAPACITANCE FOR A CAPACITANCE SENSING CHANNEL 有权

    公开(公告)号：US20210405848A1

    公开(公告)日：2021-12-30

    申请号：US17363954

    申请日：2021-06-30

    Applicant: Cypress Semiconductor Corporation

    Inventor： Denis Ellis ,  Kaveh Hosseini ,  Timothy Williams ,  Gabriel Rowe ,  Roman Ogirko ,  Brendan Lawton

    IPC: G06F3/041 ,  G06F3/044

    Abstract: A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner generates a baseline current based on a time constant of the channel input associated with the measuring of the capacitance of the element of the capacitive sense array using the programmable baseline resistor. The capacitive hardware baseliner provides the baseline current at the channel input to provide a charge for a sense capacitor. A change in the charge of the sense capacitor is provided by the baseline current indicating a presence of a tough object proximate to the element.

    NEGATIVE HIGH VOLTAGE HOT SWITCHING CIRCUIT
    9.
    发明申请
    NEGATIVE HIGH VOLTAGE HOT SWITCHING CIRCUIT 有权
    负压高压开关电路

    公开(公告)号：US20160365849A1

    公开(公告)日：2016-12-15

    申请号：US14965678

    申请日：2015-12-10

    Applicant: Cypress Semiconductor Corporation

    Inventor： Gary Peter Moscaluk ,  Bogdan I. Georgescu ,  Timothy Williams

    IPC: H03K17/0412 ,  H03K19/0185 ,  G11C16/30 ,  G11C11/22 ,  G11C17/08 ,  G11C11/417

    CPC classification number: H03K17/04123 ,  G11C5/147 ,  G11C5/148 ,  G11C7/1084 ,  G11C11/2297 ,  G11C11/417 ,  G11C16/30 ,  G11C17/08 ,  H03K3/356182 ,  H03K19/017 ,  H03K19/018507

    Abstract: A biasing circuit includes cascoded transistors including a first transistor and a second transistor. A first gate of the first transistor is coupled to a second gate of the second transistor at a first node. The circuit also includes a voltage control circuit coupled to at least one of the first transistor or the second transistor. The voltage control circuit is configured to change a voltage level of at least one of the first transistor or the second transistor to allow voltage domain transition of an output signal in view of a change in state of an input signal without ramping a supply signal of the biasing circuit.

    Abstract translation: 偏置电路包括包括第一晶体管和第二晶体管的级联晶体管。 第一晶体管的第一栅极在第一节点耦合到第二晶体管的第二栅极。 电路还包括耦合到第一晶体管或第二晶体管中的至少一个的电压控制电路。 电压控制电路被配置为改变第一晶体管或第二晶体管中的至少一个的电压电平，以便考虑到输入信号的状态变化而导致输出信号的电压域转变，而不会使输入信号的电源信号 偏置电路。

    PROVIDING A BASELINE CAPACITANCE FOR A CAPACITANCE SENSING CHANNEL
    10.
    发明申请
    PROVIDING A BASELINE CAPACITANCE FOR A CAPACITANCE SENSING CHANNEL 有权
    为电容传感通道提供基线电容

    公开(公告)号：US20160054829A1

    公开(公告)日：2016-02-25

    申请号：US14670345

    申请日：2015-03-26

    Applicant: Cypress Semiconductor Corporation

    Inventor： Denis Ellis ,  Roman Ogirko ,  Kaveh Hosseini ,  Brendan Lawton ,  Timothy Williams ,  Gabriel Rowe

    IPC: G06F3/044

    CPC classification number: G06F3/044 ,  G06F3/0416

    Abstract: A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner may generate a baseline current using a baseline capacitor and may provide the baseline current to the channel input.

    Abstract translation: 电容感测电路可以包括与测量电容式感测阵列的单位单元的电容相关联的通道输入。 电容感测电路还可以包括耦合到通道输入的电容性硬件基础设施。 电容硬件基线设备可以使用基准电容器生成基线电流，并且可以向通道输入提供基线电流。

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