公开(公告)号：US20250005418A1

公开(公告)日：2025-01-02

申请号：US18710133

申请日：2022-11-16

Applicant: D-WAVE SYSTEMS INC.

Inventor： Kelly T. R. Boothby ,  Min Jan Tsai ,  Berta Trullas Clavera ,  Mauricio Reis Filho ,  Paul I. Bunyk

IPC: G06N10/40

Abstract: A superconducting flux qubit readout system may include an input-output system connected to at least one shift register, the shift register comprising a first set, a second set, and a third set of shift register stages arranged in series, the first set of shift register stages coupled to a first set of qubits by a first plurality of latches, and the second set of shift register stages coupled to a second set of qubits by a second plurality of latches. Reading out states of a first set of qubits may include: shifting qubit state information to first holding latches communicatively coupled to a shift register; obtaining, by each shift register stage of the first set of shift register stages, state information from the first holding latches; and, propagating information along the shift register.

公开(公告)号：US20240057485A1

公开(公告)日：2024-02-15

申请号：US18268513

申请日：2021-12-16

Applicant: D-WAVE SYSTEMS INC.

Inventor： Fabio Altomare ,  Andrew J. Berkley ,  Ilya V. Perminov ,  Mauricio Reis Filho

IPC: H10N69/00 ,  H10N60/12

CPC classification number: H10N69/00 ,  H10N60/12

Abstract: A system, comprising a superconducting integrated circuit and a controller, may be operated to apply, for each power level of a sequence of discrete power levels on a respective one of a plurality of power lines, one or more pulses via a respective one of a plurality of addressing lines to a respective compound Josephson junction of each of a plurality of flux storage devices of the superconducting integrated circuit to cause each of the plurality of flux storage devices to reset. Power levels may be based at least in part on an estimated worst-case asymmetry between Josephson junctions of the compound Josephson junctions. The system may be operated to partition the plurality of addressing lines into groups, and apply a respective sequence of pulses to each addressing line of each pairwise combination of groups to cause one or more of the plurality of flux storage devices to reset.

公开(公告)号：US20220253740A1

公开(公告)日：2022-08-11

申请号：US17617388

申请日：2020-07-10

Applicant: D-WAVE SYSTEMS INC.

Inventor： Mark W. Johnson ,  Mauricio Reis Filho ,  Mark H. Volkmann ,  Ilya V. Perminov ,  Paul I. Bunyk

IPC: G06N10/20

Abstract: A digital processor simulates a quantum computing system by implementing a QPU model including a set of representation models and a device connectivity representation to simulate a quantum processor design or a physical quantum processor. The digital processor receives an analog waveform and generates a digital waveform representation comprising a set of waveform values that correspond to biases applied to programmable devices in a quantum processor. The digital processor selects a subset of waveform values based on channels in the device connectivity representation. The digital processor implements a representation model to compute a response based on the waveform values and a plurality of physical parameter values, the physical parameters characterizing a programmable device in a quantum processor. The device connectivity representation can be generated from a design implementation, validated against a set of rules, and adjusted to change the device connectivity representation until all of the rules are passed.