公开(公告)号：US11288073B2

公开(公告)日：2022-03-29

申请号：US16854396

申请日：2020-04-21

Applicant: D-WAVE SYSTEMS INC.

Inventor： Andrew J. Berkley ,  Ilya V. Perminov ,  Mark W. Johnson ,  Christopher B. Rich ,  Fabio Altomare ,  Trevor M. Lanting

IPC: G06F15/76 ,  G06F9/38 ,  G06N10/00 ,  G06F16/901 ,  H01L39/22

Abstract: A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.

公开(公告)号：US20200379768A1

公开(公告)日：2020-12-03

申请号：US16854396

申请日：2020-04-21

Applicant: D-WAVE SYSTEMS INC.

Inventor： Andrew J. Berkley ,  Ilya V. Perminov ,  Mark W. Johnson ,  Christopher B. Rich ,  Fabio Altomare ,  Trevor M. Lanting

IPC: G06F9/38 ,  G06F16/901 ,  G06N10/00

Abstract: A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.

公开(公告)号：US20240057485A1

公开(公告)日：2024-02-15

申请号：US18268513

申请日：2021-12-16

Applicant: D-WAVE SYSTEMS INC.

Inventor： Fabio Altomare ,  Andrew J. Berkley ,  Ilya V. Perminov ,  Mauricio Reis Filho

IPC: H10N69/00 ,  H10N60/12

CPC classification number: H10N69/00 ,  H10N60/12

Abstract: A system, comprising a superconducting integrated circuit and a controller, may be operated to apply, for each power level of a sequence of discrete power levels on a respective one of a plurality of power lines, one or more pulses via a respective one of a plurality of addressing lines to a respective compound Josephson junction of each of a plurality of flux storage devices of the superconducting integrated circuit to cause each of the plurality of flux storage devices to reset. Power levels may be based at least in part on an estimated worst-case asymmetry between Josephson junctions of the compound Josephson junctions. The system may be operated to partition the plurality of addressing lines into groups, and apply a respective sequence of pulses to each addressing line of each pairwise combination of groups to cause one or more of the plurality of flux storage devices to reset.

公开(公告)号：US20210384406A1

公开(公告)日：2021-12-09

申请号：US17321819

申请日：2021-05-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC: H01L39/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/18 ,  H01L39/12

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

公开(公告)号：US11957065B2

公开(公告)日：2024-04-09

申请号：US17321819

申请日：2021-05-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC: H10N60/01 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10N60/85 ,  H10N69/00

CPC classification number: H10N60/0156 ,  H01L21/76891 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53285 ,  H10N60/85 ,  H10N69/00

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

公开(公告)号：US11038095B2

公开(公告)日：2021-06-15

申请号：US16481788

申请日：2018-01-31

Applicant: D-WAVE SYSTEMS INC.

Inventor： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC: H01L27/18 ,  H01L39/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L39/12

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.