-
公开(公告)号：US20230027682A1
公开(公告)日：2023-01-26
申请号：US17786192
申请日：2020-12-15
Applicant: D-WAVE SYSTEMS INC.
Inventor： Reza Molavi , Mark H. Volkmann , Emile M. Hoskinson , Richard G. Harris , Trevor M. Lanting , Paul I. Bunyk , Andrew J. Berkley
Abstract: An analog computing system having a qubit which is provided with inductors positioned near to the qubit's Josephson junctions and inductors positioned far from the qubit's Josephson junctions. The near inductors exhibit capacitance-reducing behavior and the far inductors exhibit capacitance-increasing behavior as their respective inductances are increased. Near and far inductors can be tuned to homogenize the capacitance of the qubit across a range of programmable states based on predicted and target capacitance for the qubit. The inductors may be tuned to homogenize both capacitance and inductance.
-
公开(公告)号：US11514223B2
公开(公告)日：2022-11-29
申请号：US17068388
申请日：2020-10-12
Applicant: D-WAVE SYSTEMS INC.
Inventor： Reza Molavi , Mark H. Volkmann , Paul I. Bunyk
IPC: G06F30/398 , G06N10/00 , G06F30/392 , G06F115/12
Abstract: Systems and methods are described to accurately extract device parameters and optimize the design of macroscopic superconducting structures, for example qubits. This method presents the advantage of reusing existing plaquettes to simulate different processor topologies. The physical elements of a qubits are extracted via plurality of plaquettes. Each plaquette contains at least one physical element of the qubit design and has two ports on each side. Each plaquette is concatenated to at least one other plaquette via two ports. The values of inductance (L), capacitance (C) and mutual inductance (M) and quantum critical point of the qubit design can be computed. Changing the physical elements of the qubit design and iterating the method allows to effortlessly refine the qubit design.
-
Patent Agency Ranking
公开(公告)号：US20250055457A1
公开(公告)日：2025-02-13
申请号：US18718139
申请日：2022-12-14
Applicant: D-WAVE SYSTEMS INC.
Inventor： Jed D. Whittaker , Mark H. Volkmann , Andrew J. Berkley , Reza Molavi , Paul Bunyk , Loren J. Swenson
IPC: H03K17/92 , H03K5/1252
Abstract: A method of generating a coupling gate between qubits and a superconducting integrated circuit providing a pulse source are discussed. The method includes energizing a power line connected to a pulse source, applying a signal to a control line in communication with a coupler, the coupler in communication between the two qubits, and applying a second signal to a control line in communication with a resonator. The method further includes inducing a tone on a transmission line that selectively communicates with the resonator to bias the resonator, the resonator coupling a signal to the pulse source in combination with the power line, and applying a third signal to a pulse source control line in communication with the pulse source, the pulse source applying a pulse to the coupler in response to the third signal to couple the two qubits for a duration of the coupling gate.
-
公开(公告)号：US20240070510A1
公开(公告)日：2024-02-29
申请号：US18272235
申请日：2022-01-11
Applicant: D-WAVE SYSTEMS INC.
Inventor： Min Jan Tsai , Colin C. Enderud , Reza Molavi , Paul I. Bunyk
Abstract: Programmable components of a quantum processor may be selectively programmed using digital to analog converters (DACs). A DAC with a first stage and a second stage and first and second quantum flux parametron (OFF) loops galvanically coupled to and extending from a respective one of the first stage and the second stage is discussed. The first stage has a first storage loop interrupted by a first Josephson junction and an interface for communicating with an external component. The second stage has a second storage loop interrupted by a second Josephson junction, the second storage loop galvanically coupled to the first storage loop, the first Josephson junction and the second Josephson junction coupled in series to a first control line. A method of loading flux quanta into targeted DAC stages is also discussed.
-
公开(公告)号：US20230297869A1
公开(公告)日：2023-09-21
申请号：US18003563
申请日：2021-06-29
Applicant: D-WAVE SYSTEMS INC.
Inventor： Paul I. Bunyk , Reza Molavi , Kelly T.R. Boothby , Mark H. Volkmann
CPC classification number: G06N10/40 , H10N60/805
Abstract: A superconducting integrated circuit has a first superconducting device with a first superconducting loop, where the first superconducting loop has a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device with a second superconducting loop, where the second superconducting loop has a second superconducting trace in a second layer. The first superconducting loop crosses the second superconducting loop in a crossing region. At least a portion of each of the first and the second superconducting trace inside the crossing region is narrower than at least a portion of each of the traces outside the crossing region, and follows a respective circuitous path which is inductively proximate to at least a portion of the other path.
-
公开(公告)号：US20230101616A1
公开(公告)日：2023-03-30
申请号：US17793151
申请日：2020-12-18
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark H. Volkmann , Reza Molavi , Jed D. Whittaker
Abstract: Methods for mitigating microwave crosstalk and forming a component in a superconducting integrated circuit are discussed. Mitigating microwave crosstalk involves forming a microwave shield within the superconducting integrated circuit, the superconducting integrated circuit including a microwave sensitive component. The microwave shield is formed from a base layer and one or more sides, and the footprint of the microwave sensitive component is contained within the footprint of the microwave shielding base layer, with the one or more sides extending around at least a portion of the microwave sensitive component. Forming a component involves depositing a first metal layer, depositing a dielectric layer overlying the first metal layer, the dielectric layer comprising Nb2O5 that is deposited by atomic layer deposition, and depositing a second metal layer overlying the dielectric layer.
-
公开(公告)号：US20210133385A1
公开(公告)日：2021-05-06
申请号：US17068388
申请日：2020-10-12
Applicant: D-WAVE SYSTEMS INC.
Inventor： Reza Molavi , Mark H. Volkmann , Paul I. Bunyk
IPC: G06F30/398 , G06F30/392 , G06N10/00
Abstract: Systems and methods are described to accurately extract device parameters and optimize the design of macroscopic superconducting structures, for example qubits. This method presents the advantage of reusing existing plaquettes to simulate different processor topologies. The physical elements of a qubits are extracted via plurality of plaquettes. Each plaquette contains at least one physical element of the qubit design and has two ports on each side. Each plaquette is concatenated to at least one other plaquette via two ports. The values of inductance (L), capacitance (C) and mutual inductance (M) and quantum critical point of the qubit design can be computed. Changing the physical elements of the qubit design and iterating the method allows to effortlessly refine the qubit design.
-
-
-
-
-
-
Search Results
7
records
(took 0.02 seconds)
