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公开(公告)号：US20220207404A1
公开(公告)日：2022-06-30
申请号：US17607278
申请日：2020-06-11
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T.R. Boothby
Abstract: A quantum processor comprises a plurality of tiles, the plurality of tiles arranged in a first grid, and where a first tile of the plurality of tiles comprises a number of qubits (e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.
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公开(公告)号：US20200266234A1
公开(公告)日：2020-08-20
申请号：US16389669
申请日：2019-04-19
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T.R. Boothby , Loren J. Swenson , Mark H. Volkmann , Jed D. Whittaker
Abstract: Apparatus and methods advantageously provide parallel-plate capacitors in superconducting integrated circuits. A method may include forming a metal-oxide layer to overlie at least a portion of a first capacitor plate, the first capacitor plate comprising a superconductive material, and depositing a second capacitor plate to overlie at least a portion of the metal-oxide layer, the second capacitor plate comprising a superconductive material. The method may include depositing a base electrode of superconductive material to overlie at least a portion of a substrate, depositing the first capacitor plate to overlie at least a portion of the base electrode, and superconductingly electrically coupled to the base electrode, and depositing a counter electrode of superconductive material to overlie at least a portion of the second capacitor plate, the counter electrode superconductingly electrically coupled to the second capacitor plate. The superconducting integrated circuit may include a parallel-plate capacitor and a Josephson junction.
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公开(公告)号：US10599988B2
公开(公告)日：2020-03-24
申请号：US15448361
申请日：2017-03-02
Applicant: D-Wave Systems Inc.
Inventor： Murray C. Thom , Aidan P. Roy , Fabian A. Chudak , Zhengbing Bian , William G. Macready , Robert B. Israel , Kelly T.R. Boothby , Sheir Yarkoni , Yanbo Xue , Dmytro Korenkevych
IPC: G06N10/00
Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.
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公开(公告)号：US20200371974A1
公开(公告)日：2020-11-26
申请号：US16872595
申请日：2020-05-12
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T.R. Boothby , Andrew J. Berkley , Christopher B. Rich
Abstract: A quantum processor performs input and output which may be performed synchronously. The quantum processor executes a problem to generate a classical output state, which is read out at least partially by an I/O system. The I/O system also transmits a classical input state to by the I/O system, which may include the same qubit-proximate devices used for read-out. The classical input state is written to the qubits, and the quantum processor executes based on the classical input state (e.g., by performing reverse annealing to transform the classical input state to quantum state).
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5.发明申请公开(公告)号：US20180276550A1
公开(公告)日：2018-09-27
申请号：US15846538
申请日：2017-12-19
Applicant: D-Wave Systems Inc.
Inventor： Sheir Yarkoni , Kelly T.R. Boothby , Adam Douglass
Abstract: Quantum annealers as analog or quantum processors can find paths in problem graphs embedded in a hardware graph of the processor, for example finding valid paths, shortest paths or longest paths. A set of input, for example nucleic acid reads, can be used to set up a graph with edges between nodes denoting overlap (i.e., common base pairs) between the reads with constraints applied to perform sequence alignment or sequencing of a nucleic acid (e.g., DNA) strand or sequence, finding a solution that has a ground state energy. At least a portion of the described approaches can be applied to other problems, for instance resource allocations problems, e.g., job scheduling problems, traveling salesperson problems, and other NP-complete problems.
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Patent Agency Ranking
公开(公告)号：US20230297869A1
公开(公告)日：2023-09-21
申请号：US18003563
申请日：2021-06-29
Applicant: D-WAVE SYSTEMS INC.
Inventor： Paul I. Bunyk , Reza Molavi , Kelly T.R. Boothby , Mark H. Volkmann
CPC classification number: G06N10/40 , H10N60/805
Abstract: A superconducting integrated circuit has a first superconducting device with a first superconducting loop, where the first superconducting loop has a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device with a second superconducting loop, where the second superconducting loop has a second superconducting trace in a second layer. The first superconducting loop crosses the second superconducting loop in a crossing region. At least a portion of each of the first and the second superconducting trace inside the crossing region is narrower than at least a portion of each of the traces outside the crossing region, and follows a respective circuitous path which is inductively proximate to at least a portion of the other path.
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公开(公告)号：US20180218280A1
公开(公告)日：2018-08-02
申请号：US15881260
申请日：2018-01-26
Applicant: D-Wave Systems Inc.
Inventor： Richard G. Harris , Kelly T.R. Boothby , Andrew D. King
CPC classification number: G06N10/00 , H01L39/00 , H01L39/223 , H01L49/006
Abstract: A system and method of operation embeds a three-dimensional structure in a topology of an analog processor, for example a quantum processor. The analog processor may include a plurality of qubits arranged in tiles or cells. A number of qubits and communicatively coupled as logical qubits, each logical qubit which span across a plurality of tiles or cells of the qubits. Communicatively coupling between qubits of any given logical qubit can be implemented via application or assignment of a first ferromagnetic coupling strength to each of a number of couplers that communicatively couple the respective qubits in the logical qubit. Other ferromagnetic coupling strengths can be applied or assigned to couplers that communicatively couple qubits that are not part of the logical qubit. The first ferromagnetic coupling strength may be substantially higher than the other ferromagnetic coupling strengths.
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公开(公告)号：US20240403684A1
公开(公告)日：2024-12-05
申请号：US18735514
申请日：2024-06-06
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T.R. Boothby
Abstract: A quantum processor comprises a plurality of tiles, the plurality of tiles arranged in a first grid, and where a first tile of the plurality of tiles comprises a number of qubits (e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.
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公开(公告)号：US20220391744A1
公开(公告)日：2022-12-08
申请号：US17832327
申请日：2022-06-03
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T.R. Boothby , Peter D. Spear , Mani Ranjbar
Abstract: An accelerated version of a node-weighted path distance algorithm is implemented on a microprocessor coupled to a digital processor. The algorithm calculates an embedding of a source graph into a target graph (e.g., hardware graph of a quantum processor). The digital processor causes the microprocessor to send seeds to logic blocks with a corresponding node in the target graph contained in a working embedding of a node, compute a minimum distance to neighboring logic blocks from each seeded logic block, set the distance to neighboring logic blocks as the minimum distance plus the weight of the seeded logic block, increment the accumulator value by the weight of the seeded logic block, increment the accumulator value by the distance, determine the minimum distance logic block by computing the minimum accumulated value, compute distances to the minimum distance logic block; and read distances from all logic blocks into local memory.
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公开(公告)号：US11422958B2
公开(公告)日：2022-08-23
申请号：US16872595
申请日：2020-05-12
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T.R. Boothby , Andrew J. Berkley , Christopher B. Rich
Abstract: A quantum processor performs input and output which may be performed synchronously. The quantum processor executes a problem to generate a classical output state, which is read out at least partially by an I/O system. The I/O system also transmits a classical input state to by the I/O system, which may include the same qubit-proximate devices used for read-out. The classical input state is written to the qubits, and the quantum processor executes based on the classical input state (e.g., by performing reverse annealing to transform the classical input state to quantum state).
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