公开(公告)号：US06682943B2

公开(公告)日：2004-01-27

申请号：US09842783

申请日：2001-04-27

申请人： D. Mark Durcan ,  Gurtej Sandhu ,  Trung T. Doan ,  Roger Lee ,  Dennis Keller ,  Ren Earl

发明人： D. Mark Durcan ,  Gurtej Sandhu ,  Trung T. Doan ,  Roger Lee ,  Dennis Keller ,  Ren Earl

IPC分类号： H01G706

CPC分类号： H01L27/222

摘要： A method of forming minimally spaced MRAM structures is disclosed. A photolithography technique is employed to define masking patterns, on the sidewalls of which spacers are subsequently formed to reduce the distance between any of the two adjacent masking patterns. A filler material is next used to fill in the space around the masking patterns and to form filler plugs. The masking patterns and the spacers are removed using the filler plugs as a hard mask. Digit and word lines of MRAM structures are subsequently formed.

摘要翻译： 公开了一种形成最小间隔MRAM结构的方法。 使用光刻技术来定义掩模图案，其侧壁上随后形成间隔物以减少两个相邻掩模图案中的任一个之间的距离。 填充材料接下来用于填充掩模图案周围的空间并形成填充塞。 使用填充塞作为硬掩模去除掩模图案和间隔物。 随后形成MRAM结构的数字和字线。

公开(公告)号：US06750069B2

公开(公告)日：2004-06-15

申请号：US10454479

申请日：2003-06-05

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger Lee ,  Dennis Keller ,  Ren Earl

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger Lee ,  Dennis Keller ,  Ren Earl

IPC分类号： H01L21336

CPC分类号： H01L27/222 ,  B82Y10/00

摘要： A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.

摘要翻译： 公开了形成最小间隔的MRAM结构的方法。 使用光刻技术来定义集成电路的图案，其集成电路的宽度通过蚀刻进一步减小，以允许形成用于蚀刻具有两个数字线区域中的任一个之间的最佳临界尺寸的数字线区域的图案。 在最小间隔的数字区域上形成随后的MRAM结构的固定和感测层。

公开(公告)号：US06885051B2

公开(公告)日：2005-04-26

申请号：US10823553

申请日：2004-04-14

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger Lee ,  Dennis Keller ,  Ren Earl

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger Lee ,  Dennis Keller ,  Ren Earl

IPC分类号： H01L21/8246 ,  H01L27/22 ,  H01L31/062 ,  H01L31/036

CPC分类号： H01L27/222 ,  B82Y10/00

摘要： A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.

摘要翻译： 公开了形成最小间隔的MRAM结构的方法。 使用光刻技术来定义集成电路的图案，其集成电路的宽度通过蚀刻进一步减小，以允许形成用于蚀刻具有两个数字线区域中的任一个之间的最佳临界尺寸的数字线区域的图案。 在最小间隔的数字区域上形成随后的MRAM结构的固定和感测层。

公开(公告)号：US06689661B2

公开(公告)日：2004-02-10

申请号：US09828823

申请日：2001-04-10

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger Lee ,  Dennis Keller ,  Ren Earl

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger Lee ,  Dennis Keller ,  Ren Earl

IPC分类号： H01L21336

CPC分类号： H01L27/222 ,  B82Y10/00

摘要： A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.

摘要翻译： 公开了形成最小间隔的MRAM结构的方法。 使用光刻技术来定义集成电路的图案，其集成电路的宽度通过蚀刻进一步减小，以允许形成用于蚀刻具有两个数字线区域中的任一个之间的最佳临界尺寸的数字线区域的图案。 在最小间隔的数字区域上形成随后的MRAM结构的固定和感测层。

公开(公告)号：US07625795B2

公开(公告)日：2009-12-01

申请号：US11217742

申请日：2005-09-01

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode (“bottom electrodes”) of the structure. The etch provides a recess between proximal pairs of container capacitor structures, which is available for forming additional capacitance. A capacitor dielectric and top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Surface area common to both the first electrode and second electrodes is increased over using only the interior surface, providing additional capacitance without decreasing spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

摘要翻译： 集装箱电容器结构及其施工方法。 蚀刻掩模和蚀刻用于暴露结构的电极（“底部电极”）的外表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，其可用于形成额外的电容。 电容器电介质和顶电极分别形成在第一电极的内表面和外表面的两个部分上并与其相邻。 第一电极和第二电极两者共同的表面积仅通过使用内表面增加，提供额外的电容而不减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 电容器电介质和第二电极部分的清除可以在衬底组件的上部位置进行，与在接触通孔的底部位置处的清除相反。

公开(公告)号：US07579235B2

公开(公告)日：2009-08-25

申请号：US11545252

申请日：2006-10-10

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

公开(公告)号：US06753565B1

公开(公告)日：2004-06-22

申请号：US09652998

申请日：2000-08-31

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

IPC分类号： H01L27108

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

摘要翻译： 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

公开(公告)号：US06395600B1

公开(公告)日：2002-05-28

申请号：US09389661

申请日：1999-09-02

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L27/10811 ,  H01L27/10852 ,  H01L28/91

摘要： Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capacitor. In another embodiment, the top electrode is formed interior to, and exterior and below a portion of the bottom electrode of the container capacitor. The method of forming a top electrode of a container capacitor and a contact plug with a same deposition is particularly well-suited for high-density memory array formation.

公开(公告)号：US06329263B1

公开(公告)日：2001-12-11

申请号：US09653259

申请日：2000-08-31

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

IPC分类号： H01L2120

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

摘要翻译： 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

公开(公告)号：US07160785B1

公开(公告)日：2007-01-09

申请号：US09652999

申请日：2000-08-31

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

IPC分类号： H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

摘要翻译： 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。