公开(公告)号：US20210074631A1

公开(公告)日：2021-03-11

申请号：US17084854

申请日：2020-10-30

Applicant: DENSO CORPORATION

Inventor： Shin TAKIZAWA ,  Seiji NOMA ,  Yusuke NONAKA ,  Shinichirou YANAGI ,  Atsushi KASAHARA ,  Shogo IKEURA

IPC: H01L23/522

Abstract: On a substrate, a wiring layer is arranged by sequentially stacking a first insulation film, a lower electrode, a second insulation film, an intermediate electrode, a third insulation film, and an upper electrode in this order. A capacitor includes a first capacitor having the lower electrode and the intermediate electrode, and a second capacitor having the intermediate electrode and the upper electrode. The first capacitor and the second capacitor are connected in parallel to each other by electrically connecting the lower electrode and the upper electrode. Further, the intermediate electrode has a higher potential than the lower layer electrode and the upper electrode.

公开(公告)号：US20190279906A1

公开(公告)日：2019-09-12

申请号：US16074239

申请日：2017-03-13

Applicant: DENSO CORPORATION

Inventor： Shogo IKEURA ,  Yusuke NONAKA ,  Shinichirou YANAGI ,  Seiji NOMA ,  Shinya SAKURAI

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A buried n-type region is provided in a surface layer portion of an n-type body layer of a Pch MOSFET. This makes it possible to lower the threshold voltage Vt. In a portion of the n-type body layer other than the buried n-type region, since an n-type impurity concentration can be kept relatively high, the threshold voltage Vt can be lowered while securing an on-breakdown voltage. Furthermore, since an accumulation region is configured by an n-type active layer, a partial high concentration portion is not formed in a p-type drift layer. Therefore, as in the case where the partial high concentration portion is generated in the p-type drift layer, a reduction in a breakdown voltage caused by an electric field concentration can be restricted from occurring with a distribution in which equipotential lines are concentrated.

公开(公告)号：US20190229219A1

公开(公告)日：2019-07-25

申请号：US16368026

申请日：2019-03-28

Applicant: DENSO CORPORATION

Inventor： Shinichirou YANAGI ,  Yusuke NONAKA ,  Seiji NOMA ,  Shinya SAKURAI ,  Shogo IKEURA ,  Atsushi KASAHARA ,  Shin TAKIZAWA

IPC: H01L29/866 ,  H01L29/06 ,  H01L29/868 ,  H01L21/223 ,  H01L21/265

Abstract: A semiconductor device includes: a semiconductor substrate having a diode formation region; an upper diffusion region of a first conductivity type provided on a surface layer of a main surface of the semiconductor substrate in the diode formation region; and a lower diffusion region of a second conductivity type provided at a position deeper than the upper diffusion region with respect to the main surface in a depth direction of the semiconductor substrate, the lower diffusion region having a higher impurity concentration as compared to the semiconductor substrate. The lower diffusion region provides a PN joint surface with the upper diffusion region at a position deeper than the main surface, and has a maximum point indicating a maximum concentration in an impurity concentration profile of the lower diffusion region in the diode formation region.

公开(公告)号：US20230125063A1

公开(公告)日：2023-04-20

申请号：US18065916

申请日：2022-12-14

Applicant: DENSO CORPORATION

Inventor： Seiji NOMA ,  Tomofusa SHIGA ,  Kouji SENDA ,  Tsuyoshi NISHIWAKI ,  Yuta FURUMURA ,  Akitaka SOENO

IPC: H01L29/47 ,  H01L27/06 ,  H01L29/739 ,  H01L29/872 ,  H01L29/40

Abstract: A semiconductor device includes a semiconductor substrate and a metal film. The metal film is located on the semiconductor substrate. The metal film includes a portion to have a Schottky junction with the semiconductor substrate. The metal film is made of an aluminum alloy in which an element is added to aluminum. The metal film includes a lower metal layer and an upper metal layer. The lower metal layer is located on the semiconductor substrate. The upper metal layer stacks on the lower metal layer. The lower metal layer has a thickness of 2.6 micrometers or less in a stacking direction of the lower metal layer and the upper metal layer.

公开(公告)号：US20210005597A1

公开(公告)日：2021-01-07

申请号：US17028163

申请日：2020-09-22

Applicant: DENSO CORPORATION

Inventor： Tsuyoshi FUJIWARA ,  Seiji NOMA

IPC: H01L27/01 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor device includes a plurality of capacitors with MIM structure disposed in an interconnection layer on a substrate. Each capacitor includes a first electrode and a second electrode provided by any two interconnection parts of the interconnection layer, in which the first electrode is one of the two interconnection parts located adjacent to the substrate and the second electrode is the other located opposite to the substrate with respect to the first electrode. One of the first and second electrode of each capacitor is provided by the same interconnection part as a subject electrode, and a distance between the first electrode and the second electrode is different among the plurality of capacitors to have different capacitances. The subject electrodes provided by the same interconnection part are covered with an insulating film of the interconnection layer, and have ends on a same plane.