公开(公告)号：US20230125063A1

公开(公告)日：2023-04-20

申请号：US18065916

申请日：2022-12-14

Applicant: DENSO CORPORATION

Inventor： Seiji NOMA ,  Tomofusa SHIGA ,  Kouji SENDA ,  Tsuyoshi NISHIWAKI ,  Yuta FURUMURA ,  Akitaka SOENO

IPC: H01L29/47 ,  H01L27/06 ,  H01L29/739 ,  H01L29/872 ,  H01L29/40

Abstract: A semiconductor device includes a semiconductor substrate and a metal film. The metal film is located on the semiconductor substrate. The metal film includes a portion to have a Schottky junction with the semiconductor substrate. The metal film is made of an aluminum alloy in which an element is added to aluminum. The metal film includes a lower metal layer and an upper metal layer. The lower metal layer is located on the semiconductor substrate. The upper metal layer stacks on the lower metal layer. The lower metal layer has a thickness of 2.6 micrometers or less in a stacking direction of the lower metal layer and the upper metal layer.

公开(公告)号：US20160020310A1

公开(公告)日：2016-01-21

申请号：US14798712

申请日：2015-07-14

Applicant: DENSO CORPORATION

Inventor： Tomofusa SHIGA ,  Hiromitsu TANABE

IPC: H01L29/739 ,  H01L21/66 ,  H01L23/495 ,  H01L29/06 ,  H01L23/00 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L22/14 ,  H01L22/32 ,  H01L23/4824 ,  H01L23/49562 ,  H01L24/48 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66348 ,  H01L2224/37147 ,  H01L2224/4813 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A semiconductor device provides an element arrangement region on a semiconductor substrate including: a first semiconductor region on the semiconductor substrate; a second semiconductor region on the first semiconductor region; multiple trench gates penetrating the first semiconductor region and reaching the second semiconductor region; a third semiconductor region contacting the trench gate; a fourth semiconductor region on a rear surface; a first electrode connected to the first and second semiconductor regions; and a second electrode connected to the fourth semiconductor region. Each trench gate includes a main trench gate for generating a channel and a dummy trench gate for improving a withstand voltage of a component. The device further includes: a dummy gate wiring for applying a predetermined voltage to the dummy trench gate; and a dummy pad connected to the dummy gate wiring. The dummy pad and the first electrode are connected by a conductive member.

Abstract translation: 半导体器件在半导体衬底上提供元件布置区域，包括：半导体衬底上的第一半导体区域; 第一半导体区域上的第二半导体区域; 穿过第一半导体区域并到达第二半导体区域的多个沟槽栅极; 接触所述沟槽栅极的第三半导体区域; 在后表面上的第四半导体区域; 连接到第一和第二半导体区域的第一电极; 以及连接到第四半导体区域的第二电极。 每个沟槽栅极包括用于产生沟道的主沟槽栅极和用于提高部件的耐受电压的虚拟沟槽栅极。 该装置还包括：用于向虚拟沟槽栅极施加预定电压的虚拟栅极布线; 以及连接到虚拟栅极布线的虚拟焊盘。 虚拟焊盘和第一电极通过导电部件连接。

公开(公告)号：US20190333987A1

公开(公告)日：2019-10-31

申请号：US16504858

申请日：2019-07-08

Applicant: DENSO CORPORATION

Inventor： Masanori MIYATA ,  Shigeki TAKAHASHI ,  Masakiyo SUMITOMO ,  Tomofusa SHIGA

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/40 ,  H01L29/739

Abstract: A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.