公开(公告)号：US20090138748A1

公开(公告)日：2009-05-28

申请号：US11946466

申请日：2007-11-28

申请人： Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

发明人： Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

IPC分类号： G06F1/08

CPC分类号： G06F1/08

摘要： An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, the clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period. The apparatus further including at least one voltage drop sensor coupled to the core, the sensor being configured to generate an output signal for detecting a voltage drop in the core and to determine whether or not the output signal is detected within the clock period and, if the output signal is not detected, the sensor dynamically adjusts the clock period of the clock signal provided to the core to allow more time to complete state transitions, such that, dynamically adjusting the clock period effectively changes an effective core clock frequency.

摘要翻译： 一种用于微调微处理器中的核心的有效时钟频率的装置和方法。 该装置包括具有至少一个具有逻辑的核心的微处理器，其配置成在状态之间转换，耦合到微处理器的时钟信号，时钟信号具有基于最坏情况时钟频率和预定时钟周期的预定时钟频率。 所述装置还包括耦合到所述芯的至少一个电压降传感器，所述传感器被配置为产生用于检测所述磁芯中的电压降的输出信号，并且确定在所述时钟周期内是否检测到所述输出信号，以及如果 输出信号未检测到，传感器动态地调整提供给核心的时钟信号的时钟周期，以允许更多的时间完成状态转换，使得动态调整时钟周期有效地改变有效的核心时钟频率。

公开(公告)号：US20090138737A1

公开(公告)日：2009-05-28

申请号：US11946522

申请日：2007-11-28

申请人： Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

发明人： Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/32

摘要： An apparatus, method and program product for optimizing core performance and power in of a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized.

摘要翻译： 一种用于优化多核处理器的核心性能和功耗的设备，方法和程序产品。 该装置包括耦合到时钟源的多核处理器，其为一个或多个核心提供时钟频率，耦合到每个核心的独立电源，用于向每个核心提供电源电压，以及耦合到锁相环 到每个核心，用于动态调整提供给每个核心的时钟频率。 该装置还包括耦合到每个核心并被配置为收集针对每个核心测量的性能数据和功耗数据的控制器，并且使用PLL电路来调整提供给核心的电源电压，使得所述操作核心频率 核心大于为核心预设的规格核心频率，从而优化核心性能和功耗。

公开(公告)号：US20090134844A1

公开(公告)日：2009-05-28

申请号：US11946550

申请日：2007-11-28

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

IPC分类号： H02J7/00

CPC分类号： H02J7/345

摘要： An apparatus and method for recycling and reusing charge in an electronic circuit. The apparatus includes at least one capacitor coupled to a circuit block in the electronic circuit, the capacitor being configured to collect current charge consumed by the circuit block when set to a charge collection mode, and a voltage level comparator configured to detect a fully charged state when the capacitor is fully charged. Further, the apparatus includes a first electrical switch configured to allow, once the fully charged state is detected, the capacitor to switch to a discharge mode for discharging the current charge collected back into the power supply for reuse by the electrical system and a second switch configured to allow, after the capacitor has fully discharged the current charge collected, the capacitor to switch back to the charge collection mode, such that, the current charge is recycled and reused by the electrical system.

摘要翻译： 一种用于在电子电路中再循环和再利用电荷的装置和方法。 该装置包括耦合到电子电路中的电路块的至少一个电容器，电容器被配置为当设置为电荷收集模式时收集由电路块消耗的当前电荷;以及电压电平比较器，被配置为检测完全充电状态 当电容器充满电时。 此外，该装置包括第一电开关，其被配置为允许一旦检测到完全充电状态，电容器切换到放电模式，用于将收集的当前电荷放回电源供电系统和第二开关 配置为允许在电容器已经完全放电所收集的当前电荷之后，电容器切换回电荷收集模式，使得当前电荷被电气系统再循环和再利用。

公开(公告)号：US20080177506A1

公开(公告)日：2008-07-24

申请号：US11624329

申请日：2007-01-18

申请人： Dae Ik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

发明人： Dae Ik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

IPC分类号： G06F15/00

CPC分类号： G06F11/24 ,  G01R31/3004 ,  G01R31/31721 ,  G01R31/318505

摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.

摘要翻译： 提供了系统，方法和程序代码，用于测试多核处理器芯片结构。 单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。 在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。 核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。

公开(公告)号：US20080262777A1

公开(公告)日：2008-10-23

申请号：US12128075

申请日：2008-05-28

申请人： Dae Ik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

发明人： Dae Ik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

IPC分类号： G01R31/00 ,  G06F15/00

CPC分类号： G06F11/24 ,  G01R31/3004 ,  G01R31/31721 ,  G01R31/318505

摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.

摘要翻译： 提供了系统，方法和程序代码，用于测试多核处理器芯片结构。 单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。 在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。 核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。

公开(公告)号：US20080178023A1

公开(公告)日：2008-07-24

申请号：US11624333

申请日：2007-01-18

申请人： Dae Ik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

发明人： Dae Ik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： Systems, methods and program codes are provided for selectively adjusting multi-core processor chip structure individual processor core power supply voltages through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. Nominal power supply voltage is supplied to a first processing core, and a second core power supply voltage greater or lower than the nominal power supply voltage is supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. The second power supply voltage may be selected from ordered discrete supply voltages derived by progressively lowering the nominal supply voltage, optionally wherein the selected supply voltage also enables the second core to operate within another performance specification.

摘要翻译： 提供了系统，方法和程序代码，用于通过控制每个核心的单个电源来选择性地调整多核处理器核心电源电压的多核处理器芯片结构，以确保一个或多个内核按照一个时钟速率运行 或更多性能规格。 标称电源电压被提供给第一处理核心，并且大于或低于标称电源电压的第二核心电源电压被提供给第二处理核心，两个核心都遵守参考时钟速率规范。 第二电源电压可以从通过逐渐降低标称电源电压而导出的有序的离散电源电压中选择，可选地，其中所选择的电源电压还使得第二磁芯能够在另一性能规范内操作。

公开(公告)号：US20090132082A1

公开(公告)日：2009-05-21

申请号：US12362877

申请日：2009-01-30

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

IPC分类号： H01L29/00 ,  G06F19/00

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0073 ,  H01L23/5227 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

公开(公告)号：US20080079114A1

公开(公告)日：2008-04-03

申请号：US11536896

申请日：2006-09-29

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

IPC分类号： H01L29/00

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0073 ,  H01L23/5227 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

公开(公告)号：US20120223411A1

公开(公告)日：2012-09-06

申请号：US13469464

申请日：2012-05-11

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

IPC分类号： H01L29/86 ,  H01L21/02

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0073 ,  H01L23/5227 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

公开(公告)号：US08227891B2

公开(公告)日：2012-07-24

申请号：US12362877

申请日：2009-01-30

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

IPC分类号： H01L21/00

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0073 ,  H01L23/5227 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。