公开(公告)号：US20090161427A1

公开(公告)日：2009-06-25

申请号：US12337808

申请日：2008-12-18

申请人： Dai Nakamura ,  Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Takeshi Shimane ,  Mitsuhiro Noguchi ,  Koji Hosono ,  Masaru Koyanagi ,  Takashi Aoi

发明人： Dai Nakamura ,  Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Takeshi Shimane ,  Mitsuhiro Noguchi ,  Koji Hosono ,  Masaru Koyanagi ,  Takashi Aoi

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/24

摘要： A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

摘要翻译： 非挥发性半导体存储装置包括：具有布置在其中的存储单元的存储单元阵列，所述存储单元以非易失性方式存储数据; 以及向存储单元传送电压的多个转移晶体管，用于相对于存储单元进行数据读取，写入和擦除操作的电压。 每个转移晶体管包括：通过栅极绝缘膜形成在半导体衬底上的栅电极; 以及形成为将栅极电极夹在其间并用作漏极/源极层的扩散层。 上层布线设置在扩散层上方，并具有预定电压，以至少在传输晶体管导通时防止扩散层的耗尽。

公开(公告)号：US20080225591A1

公开(公告)日：2008-09-18

申请号：US12043510

申请日：2008-03-06

申请人： Koji Hosono ,  Masahiro Yoshihara ,  Dai Nakamura ,  Youichi Kai

发明人： Koji Hosono ,  Masahiro Yoshihara ,  Dai Nakamura ,  Youichi Kai

IPC分类号： G11C16/06 ,  G11C5/14

CPC分类号： G11C16/30 ,  G11C5/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory according to an aspect of the invention includes memory cell arrays including plural cell units, a power supply pad disposed on one end in a first direction of the memory cell arrays, and page buffers disposed in the first direction of the memory cell arrays. The nonvolatile semiconductor memory also includes plural bit lines which are disposed on the memory cell arrays while extending in the first direction and a first power supply line which is disposed on the plural bit lines on the memory cell arrays to connect the power supply pad and the page buffers.

摘要翻译： 根据本发明的一个方面的非易失性半导体存储器包括存储单元阵列，其包括多个单元单元，设置在存储单元阵列的第一方向上的一端的电源垫，以及设置在存储单元的第一方向上的页缓冲器 阵列 非易失性半导体存储器还包括多个位线，它们沿着第一方向延伸设置在存储单元阵列上，第一电源线设置在存储单元阵列上的多个位线上，以将电源焊盘和 页面缓冲区。

公开(公告)号：US08724391B2

公开(公告)日：2014-05-13

申请号：US13423610

申请日：2012-03-19

申请人： Dai Nakamura ,  Koji Hosono ,  Hidehiro Shiga

发明人： Dai Nakamura ,  Koji Hosono ,  Hidehiro Shiga

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/16 ,  G11C16/28

摘要： According to one embodiment, a semiconductor memory device includes first and second select transistors, memory cells, a driver circuit, first transfer transistors, and a detection circuit. The memory cells are stacked above a semiconductor substrate. The driver circuit outputs a first voltage. The first transfer transistors transfer the first voltage to associated word lines and select gate lines. In data erase, the detection circuit detects a second voltage applied to bit lines and/or a source line and generates a flag in accordance with the detection result. The driver circuit changes the value of the first voltage in response to the flag to cut off the first transfer transistors.

摘要翻译： 根据一个实施例，半导体存储器件包括第一和第二选择晶体管，存储单元，驱动电路，第一传输晶体管和检测电路。 存储单元堆叠在半导体衬底之上。 驱动电路输出第一电压。 第一传输晶体管将第一电压转移到相关联的字线并选择栅极线。 在数据擦除中，检测电路检测施加到位线和/或源极线的第二电压，并根据检测结果生成标志。 驱动电路响应于标志来改变第一电压的值以切断第一转移晶体管。

公开(公告)号：US07974130B2

公开(公告)日：2011-07-05

申请号：US11944803

申请日：2007-11-26

申请人： Dai Nakamura ,  Koji Hosono

发明人： Dai Nakamura ,  Koji Hosono

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344

摘要： A semiconductor memory device including a memory cell array with NAND cell units arranged therein, the NAND cell unit having a plurality of electrically rewritable and non-volatile memory cells connected in series, first and second select gate transistors disposed for coupling the both ends of the NAND cell unit to a bit line and a source line, respectively, and a dummy cell disposed adjacent to at least one of the first and second select gate transistors, wherein after erasing the memory cells in an erase unit, the memory cells excepting the dummy cell are subject to soft-program.

摘要翻译： 一种半导体存储器件，包括其中布置有NAND单元单元的存储单元阵列，所述NAND单元单元具有串联连接的多个电可重写和非易失性存储单元，第一和第二选择栅极晶体管被设置用于将 NAND单元分别连接到位线和源极线，以及与第一和第二选择栅晶体管中的至少一个相邻设置的虚设单元，其中在擦除单元中的存储单元擦除之后，除虚拟 单元格需要软件程序。

公开(公告)号：US20070206398A1

公开(公告)日：2007-09-06

申请号：US11681944

申请日：2007-03-05

申请人： Dai Nakamura ,  Koji Hosono

发明人： Dai Nakamura ,  Koji Hosono

IPC分类号： G11C16/04 ,  G11C5/02 ,  G11C16/06 ,  G11C11/34

CPC分类号： H01L27/115 ,  H01L27/11519

摘要： A semiconductor memory according to an example of the present invention is provided with a memory cell array, a plurality of word lines provided on the memory cell array, and a plurality of transfer transistors each one of which is connected to each of the plurality of word lines. Direction of one of the plurality of transfer transistors is different from direction of another one of the transfer transistors.

摘要翻译： 根据本发明的示例的半导体存储器具有存储单元阵列，设置在存储单元阵列上的多个字线，以及多个转移晶体管，每个转移晶体管中的每一个连接到多个字中的每一个 线条。 多个传输晶体管中的一个的方向与另一个传输晶体管的方向不同。

公开(公告)号：US07911844B2

公开(公告)日：2011-03-22

申请号：US12337808

申请日：2008-12-18

申请人： Dai Nakamura ,  Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Takeshi Shimane ,  Mitsuhiro Noguchi ,  Koji Hosono ,  Masaru Koyanagi ,  Takashi Aoi

发明人： Dai Nakamura ,  Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Takeshi Shimane ,  Mitsuhiro Noguchi ,  Koji Hosono ,  Masaru Koyanagi ,  Takashi Aoi

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/24

摘要： A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

摘要翻译： 非挥发性半导体存储装置包括：具有布置在其中的存储单元的存储单元阵列，所述存储单元以非易失性方式存储数据; 以及向存储单元传送电压的多个转移晶体管，用于相对于存储单元进行数据读取，写入和擦除操作的电压。 每个转移晶体管包括：通过栅极绝缘膜形成在半导体衬底上的栅电极; 以及形成为将栅极电极夹在其间并用作漏极/源极层的扩散层。 上层布线设置在扩散层上方，并具有预定电压，以至少在传输晶体管导通时防止扩散层的耗尽。

公开(公告)号：US07839679B2

公开(公告)日：2010-11-23

申请号：US12043510

申请日：2008-03-06

申请人： Koji Hosono ,  Masahiro Yoshihara ,  Dai Nakamura ,  Youichi Kai

发明人： Koji Hosono ,  Masahiro Yoshihara ,  Dai Nakamura ,  Youichi Kai

IPC分类号： G11C16/06 ,  G11C5/14

CPC分类号： G11C16/30 ,  G11C5/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory according to an aspect of the invention includes memory cell arrays including plural cell units, a power supply pad disposed on one end in a first direction of the memory cell arrays, and page buffers disposed in the first direction of the memory cell arrays. The nonvolatile semiconductor memory also includes plural bit lines which are disposed on the memory cell arrays while extending in the first direction and a first power supply line which is disposed on the plural bit lines on the memory cell arrays to connect the power supply pad and the page buffers.

摘要翻译： 根据本发明的一个方面的非易失性半导体存储器包括存储单元阵列，其包括多个单元单元，设置在存储单元阵列的第一方向上的一端的电源垫，以及设置在存储单元的第一方向上的页缓冲器 阵列 非易失性半导体存储器还包括多个位线，它们沿着第一方向延伸设置在存储单元阵列上，第一电源线设置在存储单元阵列上的多个位线上，以将电源焊盘和 页面缓冲区。

公开(公告)号：US07948797B2

公开(公告)日：2011-05-24

申请号：US12564604

申请日：2009-09-22

申请人： Yuya Suzuki ,  Dai Nakamura

发明人： Yuya Suzuki ,  Dai Nakamura

IPC分类号： G11C16/26

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： A nonvolatile semiconductor memory device comprises: a memory cell array including a plurality of memory cell units each including memory cells, a plurality of bit lines, and a common source line; a sense amplifier operative to read data from a selected memory cell; a control circuit operative to control a read operation of the sense amplifier; and a cell source monitoring circuit operative to detect a voltage of the common source line, compare the detected voltage of the common source line with a reference voltage, and output a read control signal. The sense amplifier is configured to read data from the selected memory cell through at least two cycles. The control circuit is configured to perform control to determine whether the data reading is to be ended after a first reading cycle or a second reading cycle is to be carried out, based on the read control signal.

摘要翻译： 非易失性半导体存储器件包括：存储单元阵列，包括多个存储单元单元，每个存储单元包括存储单元，多个位线和公共源极线; 读出放大器，用于从所选存储单元读取数据; 控制电路，用于控制读出放大器的读取操作; 以及电池源监视电路，用于检测公共源极线的电压，将公共源极线的检测电压与参考电压进行比较，并输出读取控制信号。 读出放大器被配置为通过至少两个周期从所选存储器单元读取数据。 控制电路被配置为基于读取的控制信号执行控制以确定在执行第一读取周期或第二读取周期之后是否结束数据读取。

公开(公告)号：US08274837B2

公开(公告)日：2012-09-25

申请号：US12727426

申请日：2010-03-19

申请人： Dai Nakamura

发明人： Dai Nakamura

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16

摘要： A NAND flash memory includes a semiconductor substrate, a well region in the semiconductor substrate, memory cells connected in series in the well region, a discharge circuit connected to the well region, a word line connected to the memory cells, and a control circuit which controls potentials of the well region and the word line. The control circuit set the well region to a first potential, and set the word line to a second potential lower than the first potential, in an erase operation. The discharge circuit comprises a constant current source with a constant discharge speed independent on a temperature, and discharges the well region after the erase operation.

摘要翻译： NAND闪存包括半导体衬底，半导体衬底中的阱区，在阱区中串联连接的存储单元，连接到阱区的放电电路，连接到存储单元的字线和控制电路， 控制井区和字线的电位。 在擦除操作中，控制电路将阱区域设置为第一电位，并将字线设置为低于第一电位的第二电位。 放电电路包括恒定的恒定电流源，其恒定的放电速度与温度无关，并且在擦除操作之后对阱区域进行放电。

公开(公告)号：US08077525B2

公开(公告)日：2011-12-13

申请号：US12537549

申请日：2009-08-07

申请人： Dai Nakamura

发明人： Dai Nakamura

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/0483

摘要： A nonvolatile semiconductor memory device includes: a memory cell array configured to have a plurality of blocks arranged thereon, each of the blocks being configured by an assembly of NAND cell units, each of the NAND cell units including a plurality of nonvolatile memory cells connected in series and word lines configured to commonly connect control gates of the memory cells. A data erase operation is executed by first applying a pre-charge voltage to the word lines, then setting to a floating state the word lines in a non-selected block where erasure of data is not to be executed, applying a certain voltage to the word lines in a selected block where erasure of data is to be executed and applying an erase voltage to a well where the memory cell array is formed, thereby altering a threshold voltage of the memory cells in the selected block.

摘要翻译： 非易失性半导体存储器件包括：存储单元阵列，被配置为具有布置在其上的多个块，每个块由NAND单元单元的组合构成，每个NAND单元单元包括多个非易失性存储单元， 串行和字线被配置为共同连接存储器单元的控制门。 执行数据擦除操作，首先对字线施加预充电电压，然后将浮动状态设置为不被执行擦除数据的未选择块中的字线，向 在要执行数据擦除的所选块中的字线，并且将擦除电压施加到形成存储单元阵列的阱中，由此改变所选块中的存储单元的阈值电压。