公开(公告)号：US5153697A

公开(公告)日：1992-10-06

申请号：US695821

申请日：1991-05-06

申请人： Dan M. Mosher ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  Larry Latham ,  David R. Cotton

发明人： Dan M. Mosher ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  Larry Latham ,  David R. Cotton

IPC分类号： H01L21/74 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/8234 ,  H01L21/8248 ,  H01L21/8249

CPC分类号： H01L21/8222 ,  H01L21/74 ,  H01L21/8226 ,  H01L21/8234 ,  H01L21/8248 ,  H01L21/8249

摘要： An integrated circuit is formed on an N-type semiconductor wafer having a first N-type epitaxial layer on the substrate, a P-type epitaxial layer over the first N-type epitaxial layer, and a second N-type epitaxial layer over the P-type epitaxial layer. There are also a plurality of sets of P-type isolation regions separating the P-type epitaxial region and the surface of the second N-type epitaxial region into epitaxial tank regions for formation of bipolar and CMOS devices, combining high power, low power, logic, switching, analog, high current, low current, digital, and linear bipolar transistors along with CMOS transistors. The characteristics of the different type of devices are combined into a single process flow.

摘要翻译： 在基板上具有第一N型外延层的N型半导体晶片上形成集成电路，在第一N型外延层上形成P型外延层，在P型上形成第二N型外延层 型外延层。 还存在将P型外延区域和第二N型外延区域的表面分离成外延槽区域以形成双极和CMOS器件的多组P型隔离区，其组合高功率，低功率， 逻辑，开关，模拟，高电流，低电流，数字和线性双极晶体管以及CMOS晶体管。 将不同类型设备的特性组合成单个流程。

公开(公告)号：US5256582A

公开(公告)日：1993-10-26

申请号：US800869

申请日：1991-11-27

申请人： Dan M. Mosher ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  Larry Latham ,  David R. Cotton ,  Bob Todd

发明人： Dan M. Mosher ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  Larry Latham ,  David R. Cotton ,  Bob Todd

IPC分类号： H01L27/06 ,  H01L21/00 ,  H01L21/02 ,  H01L21/22 ,  H01L21/26

CPC分类号： H01L27/0623 ,  Y10S148/009

摘要： The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for fabricating a high power/logic complementary bipolar/MOS/DMOS (CBiCMOS) integrated circuit. The process steps for fabricating the novel integrated circuit combines on the same substrate complementary high power, logic/analog bipolar transistors with complementary MOSGVm devices and DMOSFET devices. The present invention optimizes the characteristics of these different transistors in a single process flow. The present high power/logic CBiCMOS multiepitaxial process results in device structures having distinct technical advantages over prior art processes and structures heretofore known. For example, the present integrated circuit chip, uses bipolar power transistors instead of vertical DMOS power transistors for power applications. The bipolar power transistors are more rugged and have higher power handling capabilities than DMOS devices. Thus the bipolar transistors can be used for any out-stage configuration, including low side, high side, half bridge and full bridge output circuits. The versatility of the present process flow allows the fabrication of MOSFET, BiMOS, BiCMOS, and bipolar technology either discretely or with high power or low power NPN or PNP devices.

摘要翻译： 本发明涉及一种制造半导体集成器件的方法，更具体地说，涉及一种具有NPN和PNP功率的半导体集成器件以及与互补MOS和DMOS器件相结合的逻辑器件。 本发明是用于制造高功率/逻辑互补双极/ MOS / DMOS（CBiCMOS）集成电路的多轴工艺。 用于制造新型集成电路的工艺步骤组合在具有互补MOSGVm器件和DMOSFET器件的相同衬底互补大功率逻辑/模拟双极晶体管上。 本发明在单个工艺流程中优化这些不同晶体管的特性。 目前的高功率/逻辑CBiCMOS多外延工艺导致了与先前已知的现有技术工艺和结构相比具有不同技术优点的器件结构。 例如，本集成电路芯片采用双极型功率晶体管代替用于功率应用的垂直DMOS功率晶体管。 双极功率晶体管比DMOS器件更加坚固耐用，具有更高的功率处理能力。 因此，双极晶体管可用于任何外置配置，包括低端，高端，半桥和全桥输出电路。 本工艺流程的多功能性允许离散地或与高功率或低功率NPN或PNP器件制造MOSFET，BiMOS，BiCMOS和双极技术。

公开(公告)号：US5034337A

公开(公告)日：1991-07-23

申请号：US576136

申请日：1990-08-29

申请人： Dan M. Mosher ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  Larry Latham ,  David R. Cotton

发明人： Dan M. Mosher ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  Larry Latham ,  David R. Cotton

IPC分类号： H01L21/74 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/8234 ,  H01L21/8248 ,  H01L21/8249

CPC分类号： H01L21/8249 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/8234 ,  H01L21/8248 ,  Y10S148/011

摘要： A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.

摘要翻译： 制造涉及多个外延层生长步骤的半导体器件的工艺。

公开(公告)号：US5181095A

公开(公告)日：1993-01-19

申请号：US688196

申请日：1991-04-19

申请人： Dan M. Mosher ,  Larry Latham ,  Bob Todd ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  David R. Cotton

发明人： Dan M. Mosher ,  Larry Latham ,  Bob Todd ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  David R. Cotton

IPC分类号： H01L27/06

CPC分类号： H01L27/0623

摘要： An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.

摘要翻译： 在衬底上的第一N型外延层的集成电路器件，在第一外延层上的第二P型外延层和在第二外延层上的第三N型外延层，具有P型埋地 区域，其形成在所述衬底的一部分中，所述接地区域在第一槽区域中从所述衬底延伸到所述第三外延层并且延伸穿过所述第一和第二外延层。 功率双极晶体管形成在第一槽区中。 从第三外延层的表面延伸到P接地区的P隔离区将双极晶体管与其中形成N和P沟道MOSFET的同一衬底上的其它槽区分离。