公开(公告)号：US06440812B2

公开(公告)日：2002-08-27

申请号：US09436306

申请日：1999-11-08

申请人： Michael Violette

发明人： Michael Violette

IPC分类号： H01L21331

CPC分类号： H01L29/66272 ,  H01L21/26586 ,  H01L29/0821 ,  Y10S148/01 ,  Y10S148/011

摘要： Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by the use of an angled ion implant of collector impurities through the emitter opening. The resulting area of increased collector doping is larger than the emitter opening, which minimizes carrier injection from the emitter to the collector, but is smaller than the area of the base.

摘要翻译： 公开了用于改善双极晶体管的高电流操作同时最小化对高频响应的不利影响的方法和装置。 通过使用通过发射器开口的集电极杂质的成角度的离子注入来实现增加在集电极到基极界面处的集电极的掺杂的局部注入。 所得到的集电极掺杂增加的面积大于发射极开口，这使得从发射极到集电极的载流子注入最小化，但是小于基极的面积。

公开(公告)号：US6001701A

公开(公告)日：1999-12-14

申请号：US871385

申请日：1997-06-09

申请人： Michael Scott Carroll ,  Samir Chaudhry ,  Alan Sangone Chen ,  Yih-Feng Chyan ,  Kuo-Hua Lee ,  William John Nagy

发明人： Michael Scott Carroll ,  Samir Chaudhry ,  Alan Sangone Chen ,  Yih-Feng Chyan ,  Kuo-Hua Lee ,  William John Nagy

IPC分类号： H01L21/331 ,  H01L21/762 ,  H01L21/8249

CPC分类号： H01L29/66272 ,  H01L21/76218 ,  H01L21/8249 ,  Y10S148/009 ,  Y10S148/01 ,  Y10S148/011

摘要： A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.

摘要翻译： 公开了一种双极制造工艺，其示意性地适合于集成到常规CMOS工艺中，从而形成BiCMOS集成电路。 集电极和基极通过多个注入和单个掩模步骤形成，从而提供连续的低电阻集电区。

公开(公告)号：US5892248A

公开(公告)日：1999-04-06

申请号：US720388

申请日：1996-09-30

申请人： Aaron K. Oki ,  Donald K. Umemoto ,  Liem T. Tran ,  Dwight C. Streit

发明人： Aaron K. Oki ,  Donald K. Umemoto ,  Liem T. Tran ,  Dwight C. Streit

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737 ,  H01L31/0328 ,  H01L27/082 ,  H01L31/0336

CPC分类号： H01L29/66318 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/072 ,  Y10S148/10 ,  Y10S148/143

摘要： A heterojunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.

摘要翻译： 异相结双极晶体管和使用双光致抗蚀剂制造具有自对准基底金属触点的HBT的方法，其比已知方法需要更少的工艺步骤，同时最小化对有源发射极接触区域的损害。 特别地，光致抗蚀剂用于形成发射台台面。 留下发射台面光致抗蚀剂，然后施加双重聚甲基丙烯酸甲酯（PMMA）和光致抗蚀剂层。 将三重光致抗蚀剂组合图案化以产生用于基底金属接触到发射极台面的非关键侧向对准，这允许选择性基极欧姆金属沉积和剥离。 通过利用双光致抗蚀剂与用于掩蔽的金属或电介质相反，消除了额外的光刻步骤和蚀刻步骤。 通过消除对另外的蚀刻步骤的需要，可以防止半导体的有源区暴露于蚀刻步骤并且可能被损坏。

公开(公告)号：US5856697A

公开(公告)日：1999-01-05

申请号：US895270

申请日：1997-07-14

申请人： Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

发明人： Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/0804 ,  Y10S148/01 ,  Y10S148/011

摘要： A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

摘要翻译： 公开了一种从双极晶体管的基极区域隔离多晶硅发射极的新方法，将多晶硅发射极沟槽到半导体衬底中，并保持独立于发射极掩模厚度变化的双极晶体管的一致的基底宽度。 多晶硅发射极隔离通过保护多晶硅发射极和基极区域之间的电介质层与BiCMOS制造环境相关的缺陷和污染来提供发射极和基极之间的更好的电击穿特性。 为了减少与热电子注入相关的晶体管操作问题，多晶硅发射极被沟入半导体衬底。 一致的基极宽度提高了晶体管的性能均匀性，从而提高了可制造性和可靠性。

公开(公告)号：US5856228A

公开(公告)日：1999-01-05

申请号：US757335

申请日：1996-11-27

申请人： Hiroyuki Miwa ,  Shigeru Kanematsu ,  Takayuki Gomi ,  Hiroaki Anmo ,  Takashi Noguchi ,  Katsuyuki Kato ,  Hirokazu Ejiri ,  Norikazu Ouchi

发明人： Hiroyuki Miwa ,  Shigeru Kanematsu ,  Takayuki Gomi ,  Hiroaki Anmo ,  Takashi Noguchi ,  Katsuyuki Kato ,  Hirokazu Ejiri ,  Norikazu Ouchi

IPC分类号： H01L21/331 ,  H01L29/732

CPC分类号： H01L29/7322 ,  H01L29/66272 ,  Y10S148/01 ,  Y10S148/011

摘要： A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

摘要翻译： 一种半导体器件及其制造方法，其可以通过减小基极宽度同时实现基极通过时间的减少，并且通过降低基极电阻降低基极电阻。 半导体器件通过包括以下步骤的方法制造：在半导体衬底中形成第一导电类型的第一杂质扩散层; 形成连接到第一杂质扩散层的导电膜; 在导电膜上形成第一绝缘膜; 通过由第一绝缘膜和导电膜构成的层压膜形成第一孔; 在暴露于第一孔的半导体衬底中形成第一导电类型的第二杂质扩散层; 从所述第一孔中的第二绝缘膜形成侧壁以形成第二孔; 以及在暴露于第二孔的半导体衬底中形成第一导电类型的第三杂质扩散层。

公开(公告)号：US5736417A

公开(公告)日：1998-04-07

申请号：US647609

申请日：1996-05-13

申请人： Aaron K. Oki ,  Donald K. Umemoto ,  Liem T. Tran ,  Dwight C. Streit

发明人： Aaron K. Oki ,  Donald K. Umemoto ,  Liem T. Tran ,  Dwight C. Streit

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737 ,  H01L21/265

CPC分类号： H01L29/66318 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/072 ,  Y10S148/10 ,  Y10S148/143

摘要： A heterejunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.

摘要翻译： 双极性晶体管和使用双光致抗蚀剂制造具有自对准基底金属触点的HBT的方法，其需要比已知方法更少的工艺步骤，同时最小化对有源发射极接触区域的损害。 特别地，光致抗蚀剂用于形成发射台台面。 留下发射台面光致抗蚀剂，然后施加双重聚甲基丙烯酸甲酯（PMMA）和光致抗蚀剂层。 将三重光致抗蚀剂组合图案化以产生用于基底金属接触到发射极台面的非关键侧向对准，这允许选择性基极欧姆金属沉积和剥离。 通过利用双光致抗蚀剂与用于掩蔽的金属或电介质相反，消除了额外的光刻步骤和蚀刻步骤。 通过消除对另外的蚀刻步骤的需要，可以防止半导体的有源区暴露于蚀刻步骤并且可能被损坏。

公开(公告)号：US5719082A

公开(公告)日：1998-02-17

申请号：US519817

申请日：1995-08-25

申请人： Michael Violette

发明人： Michael Violette

IPC分类号： H01L21/265 ,  H01L21/331 ,  H01L29/08

CPC分类号： H01L29/66272 ,  H01L21/26586 ,  H01L29/0821 ,  Y10S148/01 ,  Y10S148/011

摘要： Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by the use of an angled ion implant of collector impurities through the emitter opening. The resulting area of increased collector doping is larger than the emitter opening, which minimizes carrier injection from the emitter to the collector, but is smaller than the area of the base.

公开(公告)号：US5681763A

公开(公告)日：1997-10-28

申请号：US581665

申请日：1995-12-29

申请人： Thomas Edward Ham ,  Isik C. Kizilyalli

发明人： Thomas Edward Ham ,  Isik C. Kizilyalli

IPC分类号： H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L29/10 ,  H01L29/167 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/26513 ,  H01L29/1004 ,  H01L29/167 ,  Y10S148/01 ,  Y10S148/011

摘要： Indium doping is used to make bases of bipolar transistors with superior operational characteristics.

摘要翻译： 铟掺杂用于制造具有卓越操作特性的双极晶体管的基极。

公开(公告)号：US5670394A

公开(公告)日：1997-09-23

申请号：US317155

申请日：1994-10-03

申请人： Rick C. Jerome ,  Ian R. C. Post

发明人： Rick C. Jerome ,  Ian R. C. Post

IPC分类号： H01L21/225 ,  H01L21/331 ,  H01L21/8228 ,  H01L21/265

CPC分类号： H01L29/66272 ,  H01L21/2257 ,  H01L21/8228 ,  Y10S148/01 ,  Y10S148/011

摘要： The present invention teaches a method for fabricating a bipolar junction transistor ("BJT") from a semiconductor substrate having a base region, wherein the BJT comprises an increased Early voltage. The method initially comprises the step of forming a patterned interlevel dielectric layer superjacent the substrate such that a segment of the substrate is exposed. Subsequently, a contact comprising a material having a grain size smaller than polycrystalline silicon is formed superjacent the patterned interlevel dielectric layer and the segment of the substrate exposed. The contact is then implanted with a dopant. Once implanted, the substrate is annealed to enable the dopant to diffuse from the contact into the base region impeded by the grain size to form an emitter region and thereby increase the Early voltage of the bipolar junction transistor.

摘要翻译： 本发明教导了一种从具有基极区域的半导体衬底制造双极结型晶体管（“BJT”）的方法，其中BJT包括增加的早期电压。 该方法最初包括以下步骤：在衬底之上形成图案化的层间电介质层，使得衬底的一部分被暴露。 随后，包含具有小于多晶硅的晶粒尺寸的材料的触点形成在图案化的层间电介质层的上方，并且衬底的部分被暴露。 然后用掺杂剂注入接触。 一旦被植入，衬底被退火以使掺杂剂从接触扩散到由晶粒尺寸阻挡的基极区域中，以形成发射极区域，从而增加双极结型晶体管的早期电压。

公开(公告)号：US5593905A

公开(公告)日：1997-01-14

申请号：US392597

申请日：1995-02-23

申请人： F. Scott Johnson ,  Kelly Taylor

发明人： F. Scott Johnson ,  Kelly Taylor

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/10 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L29/66272 ,  H01L29/1004 ,  Y10S148/01 ,  Y10S148/011

摘要： A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A barrier layer (119) is formed over the base-link diffusion source layer (118).A base electrode (114) is formed over at least one end portion of the barrier layer (119) and base-link diffusion source layer (118) and the exposed portions of the barrier layer (119) and underlying base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to fore an intrinsic base region (108), emitter region (126), and emitter electrode (124).

摘要翻译： 双极晶体管（100）及其形成方法。 在集电极区域（102）的一部分上形成基极 - 链路扩散源层（118）。 基极 - 链路扩散源层（118）包括能够用作掺杂剂源并且能够相对于硅选择性蚀刻的材料。 在该基极连接扩散源层（118）的上方形成阻挡层（119）。在阻挡层（119）的至少一个端部与基极扩散源层（118）的至少一个端部形成有基极 ）并且去除了阻挡层（119）和下面的基底 - 链路扩散源层（118）的暴露部分。 外部基极区域（110）从基极（114）扩散，基极连接区域（112）从基极扩散源层（118）扩散。 然后处理可以继续在本征基区（108），发射极区（126）和发射极（124）之前。