公开(公告)号：US5256582A

公开(公告)日：1993-10-26

申请号：US800869

申请日：1991-11-27

申请人： Dan M. Mosher ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  Larry Latham ,  David R. Cotton ,  Bob Todd

发明人： Dan M. Mosher ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  Larry Latham ,  David R. Cotton ,  Bob Todd

IPC分类号： H01L27/06 ,  H01L21/00 ,  H01L21/02 ,  H01L21/22 ,  H01L21/26

CPC分类号： H01L27/0623 ,  Y10S148/009

摘要： The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for fabricating a high power/logic complementary bipolar/MOS/DMOS (CBiCMOS) integrated circuit. The process steps for fabricating the novel integrated circuit combines on the same substrate complementary high power, logic/analog bipolar transistors with complementary MOSGVm devices and DMOSFET devices. The present invention optimizes the characteristics of these different transistors in a single process flow. The present high power/logic CBiCMOS multiepitaxial process results in device structures having distinct technical advantages over prior art processes and structures heretofore known. For example, the present integrated circuit chip, uses bipolar power transistors instead of vertical DMOS power transistors for power applications. The bipolar power transistors are more rugged and have higher power handling capabilities than DMOS devices. Thus the bipolar transistors can be used for any out-stage configuration, including low side, high side, half bridge and full bridge output circuits. The versatility of the present process flow allows the fabrication of MOSFET, BiMOS, BiCMOS, and bipolar technology either discretely or with high power or low power NPN or PNP devices.

摘要翻译： 本发明涉及一种制造半导体集成器件的方法，更具体地说，涉及一种具有NPN和PNP功率的半导体集成器件以及与互补MOS和DMOS器件相结合的逻辑器件。 本发明是用于制造高功率/逻辑互补双极/ MOS / DMOS（CBiCMOS）集成电路的多轴工艺。 用于制造新型集成电路的工艺步骤组合在具有互补MOSGVm器件和DMOSFET器件的相同衬底互补大功率逻辑/模拟双极晶体管上。 本发明在单个工艺流程中优化这些不同晶体管的特性。 目前的高功率/逻辑CBiCMOS多外延工艺导致了与先前已知的现有技术工艺和结构相比具有不同技术优点的器件结构。 例如，本集成电路芯片采用双极型功率晶体管代替用于功率应用的垂直DMOS功率晶体管。 双极功率晶体管比DMOS器件更加坚固耐用，具有更高的功率处理能力。 因此，双极晶体管可用于任何外置配置，包括低端，高端，半桥和全桥输出电路。 本工艺流程的多功能性允许离散地或与高功率或低功率NPN或PNP器件制造MOSFET，BiMOS，BiCMOS和双极技术。

公开(公告)号：US5153697A

公开(公告)日：1992-10-06

申请号：US695821

申请日：1991-05-06

申请人： Dan M. Mosher ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  Larry Latham ,  David R. Cotton

发明人： Dan M. Mosher ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  Larry Latham ,  David R. Cotton

IPC分类号： H01L21/74 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/8234 ,  H01L21/8248 ,  H01L21/8249

CPC分类号： H01L21/8222 ,  H01L21/74 ,  H01L21/8226 ,  H01L21/8234 ,  H01L21/8248 ,  H01L21/8249

摘要： An integrated circuit is formed on an N-type semiconductor wafer having a first N-type epitaxial layer on the substrate, a P-type epitaxial layer over the first N-type epitaxial layer, and a second N-type epitaxial layer over the P-type epitaxial layer. There are also a plurality of sets of P-type isolation regions separating the P-type epitaxial region and the surface of the second N-type epitaxial region into epitaxial tank regions for formation of bipolar and CMOS devices, combining high power, low power, logic, switching, analog, high current, low current, digital, and linear bipolar transistors along with CMOS transistors. The characteristics of the different type of devices are combined into a single process flow.

摘要翻译： 在基板上具有第一N型外延层的N型半导体晶片上形成集成电路，在第一N型外延层上形成P型外延层，在P型上形成第二N型外延层 型外延层。 还存在将P型外延区域和第二N型外延区域的表面分离成外延槽区域以形成双极和CMOS器件的多组P型隔离区，其组合高功率，低功率， 逻辑，开关，模拟，高电流，低电流，数字和线性双极晶体管以及CMOS晶体管。 将不同类型设备的特性组合成单个流程。

公开(公告)号：US5034337A

公开(公告)日：1991-07-23

申请号：US576136

申请日：1990-08-29

申请人： Dan M. Mosher ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  Larry Latham ,  David R. Cotton

发明人： Dan M. Mosher ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  Larry Latham ,  David R. Cotton

IPC分类号： H01L21/74 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/8234 ,  H01L21/8248 ,  H01L21/8249

CPC分类号： H01L21/8249 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/8234 ,  H01L21/8248 ,  Y10S148/011

摘要： A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.

摘要翻译： 制造涉及多个外延层生长步骤的半导体器件的工艺。

公开(公告)号：US5181095A

公开(公告)日：1993-01-19

申请号：US688196

申请日：1991-04-19

申请人： Dan M. Mosher ,  Larry Latham ,  Bob Todd ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  David R. Cotton

发明人： Dan M. Mosher ,  Larry Latham ,  Bob Todd ,  Cornelia H. Blanton ,  Joe R. Trogolo ,  David R. Cotton

IPC分类号： H01L27/06

CPC分类号： H01L27/0623

摘要： An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.

摘要翻译： 在衬底上的第一N型外延层的集成电路器件，在第一外延层上的第二P型外延层和在第二外延层上的第三N型外延层，具有P型埋地 区域，其形成在所述衬底的一部分中，所述接地区域在第一槽区域中从所述衬底延伸到所述第三外延层并且延伸穿过所述第一和第二外延层。 功率双极晶体管形成在第一槽区中。 从第三外延层的表面延伸到P接地区的P隔离区将双极晶体管与其中形成N和P沟道MOSFET的同一衬底上的其它槽区分离。

公开(公告)号：US5267118A

公开(公告)日：1993-11-30

申请号：US843701

申请日：1992-02-28

申请人： Andrew Marshall ,  Kenneth G. Buss ,  David R. Cotton

发明人： Andrew Marshall ,  Kenneth G. Buss ,  David R. Cotton

IPC分类号： H02H5/04

CPC分类号： H02H5/044

摘要： Circuitry (46, or 28 and 70) for thermally separating a power integrated circuit device (12) from a plurality of other such devices (14, 16, and 18) on a common power integrated circuit chip (10) operate when the device (12) reaches a thermal shutdown temperature setpoint (56) with an output current at a predetermined current limit (54). The circuitry 46, or 28 and 70 switches the output current to a shutdown current level (57) until the device (12) reaches a predetermined lower temperature setpoint (58). Circuitry (46, or 28 and 70) restores the output current level to the predetermined current limit only after the device (12) reaches both the predetermined lower temperature setpoint (58) and a predetermined circuit setpoint (62 or 74). The circuit setpoint (62 or 74) associates with the temperature of the device (12) and may be either a yet lower temperature setpoint (62) or a specified time delay (74). The above steps are repeated to lower the average temperature of the device (12) and thereby thermally separate the device (12) from the other of such devices (14, 16 and 18) on the common power integrated circuit chip (10).

摘要翻译： 用于将功率集成电路器件（12）与公共功率集成电路芯片（10）上的多个其它这样的器件（14,16和18）热分离的电路（46或28和70）在器件 12）以预定电流极限（54）的输出电流达到热关断温度设定点（56）。 电路46或28和70将输出电流切换到关断电流电平（57），直到装置（12）达到预定的较低温度设定点（58）。 只有在设备（12）达到预定的较低温度设定点（58）和预定的电路设定点（62或74）之后，电路（46或28和70）才将输出电流电平恢复到预定电流限制。 电路设定点（62或74）与设备（12）的温度相关联，并且可以是较低温度设定点（62）或指定的时间延迟（74）。 重复上述步骤以降低装置（12）的平均温度，从而将装置（12）与公共功率集成电路芯片（10）上的另一个装置（14,16和18）热分离。

公开(公告)号：US5036377A

公开(公告)日：1991-07-30

申请号：US227961

申请日：1988-08-03

申请人： Vijay K. Pathak ,  David R. Cotton

发明人： Vijay K. Pathak ,  David R. Cotton

IPC分类号： H01L29/747

CPC分类号： H01L29/747

摘要： Thyristors of one conductivity type formed as an array in a first semiconductor body are respectively connected in parallel with thyristors of the opposite conductivity type formed as an array in a second semiconductor body to produce an array of triacs. In each body the thyristors are separate except for a common anode or cathode region and terminal connection, and are formed in an epitaxial layer divided by PN junction isolation regions on a substrate of opposite conductivity type. The thyristors may be constructed to be triggered by gating signals of either polarity.

摘要翻译： 在第一半导体本体中形成为阵列的一种导电类型的晶体管分别与在第二半导体本体中作为阵列形成的相反导电类型的晶闸管并联连接以产生三端双向可控硅开关元件阵列。 在每个主体中，除了公共阳极或阴极区域和端子连接之外，晶闸管是分离的，并且形成在由相反导电类型的衬底上的PN结隔离区域划分的外延层中。 晶闸管可以构造成由任一极性的选通信号触发。

公开(公告)号：US4604640A

公开(公告)日：1986-08-05

申请号：US656216

申请日：1984-10-01

申请人： Derek Colman ,  David R. Cotton

发明人： Derek Colman ,  David R. Cotton

IPC分类号： H01L27/082 ,  H01L27/02 ,  H01L27/04 ,  H03K3/26

CPC分类号： H01L27/0825

摘要： In a darlington transistor having an integrated resistor connected from base to emitter of the output transistor element, the effect of the diode between collector and emitter formed when the resistor consists of an extension to the base region is reduced by forming at least part of the resistor either as an extension to the emitter region or as a separate region of the same conductivity type and connected to it. The resistor formed by the emitter region material appears in series with the diode.

摘要翻译： 在具有从输出晶体管元件的基极到发射极连接的集成电阻器的达林顿晶体管中，当电阻器由基极区域延伸而形成的集电极和发射极之间形成的二极管的影响通过形成电阻器的至少一部分而减小 作为发射极区域的延伸或作为相同导电类型的单独区域并与其连接。 由发射极区域材料形成的电阻与二极管串联。

公开(公告)号：US5119162A

公开(公告)日：1992-06-02

申请号：US454811

申请日：1989-12-19

申请人： James R. Todd ,  David R. Cotton ,  Taylor R. Efland ,  John K. Lee ,  Roy C. Jones, III

发明人： James R. Todd ,  David R. Cotton ,  Taylor R. Efland ,  John K. Lee ,  Roy C. Jones, III

IPC分类号： H01L27/04 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L21/823456 ,  H01L21/8249 ,  H01L27/0255 ,  H01L27/0623 ,  H01L29/7802 ,  H01L29/7809

摘要： Methods and circuits of integrated DMOS, CMOS, NPN, and PNP devices include self-aligned DMOS (411) with increased breakdown voltage and ruggedness for recovery from transients including additional Zener diodes (402/474).

摘要翻译： 集成DMOS，CMOS，NPN和PNP器件的方法和电路包括具有增加的击穿电压的自对准DMOS（411）和用于从包括额外的齐纳二极管（402/474）的瞬态恢复的耐用性。

公开(公告)号：US4769688A

公开(公告)日：1988-09-06

申请号：US73861

申请日：1987-07-16

申请人： David R. Cotton

发明人： David R. Cotton

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/73 ,  H01L29/732 ,  H01L29/72 ,  H01L27/02

CPC分类号： H01L29/0692 ,  H01L29/7304

摘要： A bipolar power transistor having a plurality of elongated emitter parts connected to a common emitter metallization is provided with a shaped resistive region between the emitter parts and the emitter metallization, in order to compensate for differences in the resistance presented by the metallization itself.

摘要翻译： 具有连接到公共发射极金属化的多个细长发射极部分的双极功率晶体管在发射极部分和发射极金属化之间设置有形状的电阻区域，以补偿由金属化本身呈现的电阻的差异。