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    Landing Pad for Use As a Contact to a Conductive Spacer
    1.
    发明申请
    Landing Pad for Use As a Contact to a Conductive Spacer 有权
    用作导电间隔物接触的着陆垫

    公开(公告)号：US20090061547A1

    公开(公告)日：2009-03-05

    申请号：US12266443

    申请日：2008-11-06

    申请人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

    发明人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

    IPC分类号： H01L21/66

    CPC分类号： H01L21/76895

    摘要： A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

    摘要翻译： 用作与半导体器件中的结构相邻的导电间隔件的接触件的接合焊盘包括两个岛，每个岛基本上为矩形并且彼此间隔开并且与该结构隔开。 导电间隔件与每个岛相邻并且彼此重叠并与邻近结构的导电间隔物重叠。 与着陆垫的接触在邻近岛的导电间隔物上并且与结构间隔开。

    Landing pad for use as a contact to a conductive spacer
    2.
    发明授权
    Landing pad for use as a contact to a conductive spacer 有权
    用作与导电间隔物接触的着陆垫

    公开(公告)号：US07749779B2

    公开(公告)日：2010-07-06

    申请号：US12266443

    申请日：2008-11-06

    申请人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

    发明人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

    IPC分类号： H01L21/66

    CPC分类号： H01L21/76895

    摘要： A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

    摘要翻译： 用作与半导体器件中的结构相邻的导电间隔件的接触件的接合焊盘包括两个岛，每个岛基本上为矩形并且彼此间隔开并且与该结构隔开。 导电间隔件与每个岛相邻并且彼此重叠并与邻近结构的导电间隔物重叠。 与着陆垫的接触在邻近岛的导电间隔物上并且与结构间隔开。

    Landing pad for use as a contact to a conductive spacer
    3.
    发明授权
    Landing pad for use as a contact to a conductive spacer 有权
    用作与导电间隔物接触的着陆垫

    公开(公告)号：US06960803B2

    公开(公告)日：2005-11-01

    申请号：US10693067

    申请日：2003-10-23

    申请人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

    发明人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

    IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L29/76

    CPC分类号： H01L21/76895

    摘要： A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

    摘要翻译： 用作与半导体器件中的结构相邻的导电间隔件的接触件的接合焊盘包括两个岛，每个岛基本上为矩形并且彼此间隔开并且与该结构隔开。 导电间隔件与每个岛相邻并且彼此重叠并与邻近结构的导电间隔物重叠。 与着陆垫的接触在邻近岛的导电间隔物上并且与结构间隔开。

    Method of detecting one or more defects in a string of spaced apart studs
    4.
    发明申请
    Method of detecting one or more defects in a string of spaced apart studs 审中-公开
    检测一串间隔开的螺柱中的一个或多个缺陷的方法

    公开(公告)号：US20060014339A1

    公开(公告)日：2006-01-19

    申请号：US11221161

    申请日：2005-09-06

    申请人： Dana Lee ,  Wen-Juei Lu ,  Felix Tsui

    发明人： Dana Lee ,  Wen-Juei Lu ,  Felix Tsui

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76895

    摘要： A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

    摘要翻译： 用作与半导体器件中的结构相邻的导电间隔件的接触件的接合焊盘包括两个岛，每个岛基本上为矩形并且彼此间隔开并且与该结构隔开。 导电间隔件与每个岛相邻并且彼此重叠并与邻近结构的导电间隔物重叠。 与着陆垫的接触在邻近岛的导电间隔物上并且与结构间隔开。

    Landing pad for use as a contact to a conductive spacer
    5.
    发明申请
    Landing pad for use as a contact to a conductive spacer 有权

    公开(公告)号：US20050090063A1

    公开(公告)日：2005-04-28

    申请号：US10693067

    申请日：2003-10-23

    申请人： Dana Lee ,  Wen-Juei Lu ,  Felix Tsui

    发明人： Dana Lee ,  Wen-Juei Lu ,  Felix Tsui

    IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L29/76

    CPC分类号： H01L21/76895

    摘要： A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

    A METHOD OF MAKING A SPLIT GATE NON-VOLATILE FLOATING GATE MEMORY CELL HAVING A SEPARATE ERASE GATE, AND A MEMORY CELL MADE THEREBY
    6.
    发明申请
    A METHOD OF MAKING A SPLIT GATE NON-VOLATILE FLOATING GATE MEMORY CELL HAVING A SEPARATE ERASE GATE, AND A MEMORY CELL MADE THEREBY 有权
    制造具有单独擦除闸门的分离栅门非挥发性闸门存储单元的方法及其存储单元

    公开(公告)号：US20140217489A1

    公开(公告)日：2014-08-07

    申请号：US14240440

    申请日：2012-08-08

    申请人： Chunming Wang ,  Baowei Qiao ,  Zufa Zhang ,  Yi Zhang ,  Shiuh luen Wang ,  Wen-Juei Lu

    发明人： Chunming Wang ,  Baowei Qiao ,  Zufa Zhang ,  Yi Zhang ,  Shiuh luen Wang ,  Wen-Juei Lu

    IPC分类号： H01L29/788 ,  H01L29/66

    CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/66833

    摘要： A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall. The second side wall and the upper surface form a sharp edge, with the second side wall greater in length than the first side wall. The upper surface slopes upward from the first side wall to the second side wall. A coupling gate is positioned over the upper surface of the floating gate and is insulated therefrom by a third insulating layer. An erase gate is positioned adjacent to the second side wall of the floating gate. The erase gate is positioned over the second region and insulated therefrom.

    摘要翻译： 非易失性存储单元具有具有顶表面的第一导电类型的单晶衬底。 第二导电类型的第一区域沿着顶表面在衬底中。 第二导电类型的第二区域沿着顶表面在与第一区域间隔开的衬底中。 通道区域是第一区域和第二区域。 字线门位于与第一区域紧邻的沟道区域的第一部分上方。 字线栅极通过第一绝缘层与沟道区间隔开。 浮动栅极位于通道区域的另一部分上。 浮栅具有通过第二绝缘层与沟道区分离的下表面和与下表面相对的上表面。 浮栅具有与字线门相邻但与字线门隔开的第一侧壁; 以及与第一侧壁相对的第二侧壁。 第二侧壁和上表面形成锋利的边缘，第二侧壁的长度大于第一侧壁。 上表面从第一侧壁向上倾斜到第二侧壁。 耦合栅极位于浮动栅极的上表面上方，并通过第三绝缘层与其隔离。 擦除栅极位于浮动栅极的第二侧壁附近。 擦除栅极定位在第二区域上并与之绝缘。

    Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate and pointed channel region
    7.
    发明申请
    Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate and pointed channel region 有权
    形成具有埋置浮栅和尖通道区域的浮栅存储器单元的半导体存储器阵列的自对准方法

    公开(公告)号：US20050199914A1

    公开(公告)日：2005-09-15

    申请号：US11070079

    申请日：2005-03-01

    申请人： Bomy Chen ,  Ying Tsui ,  Wen-Juei Lu

    发明人： Bomy Chen ,  Ying Tsui ,  Wen-Juei Lu

    IPC分类号： H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/73

    CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

    摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.

    摘要翻译： 一种形成浮置栅极存储单元阵列的方法，以及由此形成的阵列，其中沟槽形成在半导体衬底的表面中。 源极区形成在沟槽下方，漏极区沿着衬底表面形成，并且其间的沟道区包括沿着沟槽侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 浮动栅极设置在与沟道区域第一部分相邻并与沟槽区域第一部分绝缘的沟槽中。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘。 沟槽侧壁以锐角与衬底表面相接触以形成锋利的边缘。 沟道区域第二部分从朝向尖锐边缘的方向从第二区域延伸，并且浮置栅极限定用于通过热电子注入用电子编程浮动栅极的路径。

    Semiconductor memory array of floating gate memory cells with burried floating gate and pointed channel region
    8.
    发明授权
    Semiconductor memory array of floating gate memory cells with burried floating gate and pointed channel region 有权
    半导体存储器阵列的浮动栅极存储器单元具有埋入浮栅和尖通道区

    公开(公告)号：US06873006B2

    公开(公告)日：2005-03-29

    申请号：US10393896

    申请日：2003-03-21

    申请人： Bomy Chen ,  Ying Kit Tsui ,  Wen-Juei Lu

    发明人： Bomy Chen ,  Ying Kit Tsui ,  Wen-Juei Lu

    IPC分类号： H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

    摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.

    摘要翻译： 一种形成浮置栅极存储单元阵列的方法，以及由此形成的阵列，其中沟槽形成在半导体衬底的表面中。 源极区形成在沟槽下方，漏极区沿着衬底表面形成，并且其间的沟道区包括沿着沟槽侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 浮动栅极设置在与沟道区域第一部分相邻并与沟槽区域第一部分绝缘的沟槽中。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘。 沟槽侧壁以锐角与衬底表面相接触以形成锋利的边缘。 沟道区域第二部分从朝向尖锐边缘的方向从第二区域延伸，并且浮置栅极限定用于通过热电子注入用电子编程浮动栅极的路径。

    Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate and pointed channel region
    9.
    发明授权
    Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate and pointed channel region 有权
    形成具有埋置浮栅和尖通道区域的浮栅存储器单元的半导体存储器阵列的自对准方法

    公开(公告)号：US07208376B2

    公开(公告)日：2007-04-24

    申请号：US11070079

    申请日：2005-03-01

    申请人： Bomy Chen ,  Ying Kit Tsui ,  Wen-Juei Lu

    发明人： Bomy Chen ,  Ying Kit Tsui ,  Wen-Juei Lu

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

    摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.

    摘要翻译： 一种形成浮置栅极存储单元阵列的方法，以及由此形成的阵列，其中沟槽形成在半导体衬底的表面中。 源极区形成在沟槽下方，漏极区沿着衬底表面形成，并且其间的沟道区包括沿着沟槽侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 浮动栅极设置在与沟道区域第一部分相邻并与沟槽区域第一部分绝缘的沟槽中。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘。 沟槽侧壁以锐角与衬底表面相接触以形成锋利的边缘。 沟道区域第二部分从朝向尖锐边缘的方向从第二区域延伸，并且浮置栅极限定用于通过热电子注入用电子编程浮动栅极的路径。

    Process for self aligning a source region with a field oxide region and a polysilicon gate
    10.
    发明授权
    Process for self aligning a source region with a field oxide region and a polysilicon gate 失效
    用于使源区域与场氧化物区域和多晶硅栅极自对准的工艺

    公开(公告)号：US5120671A

    公开(公告)日：1992-06-09

    申请号：US621284

    申请日：1990-11-29

    申请人： Daniel N. Tang ,  Wen-Juei Lu

    发明人： Daniel N. Tang ,  Wen-Juei Lu

    IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8247

    CPC分类号： H01L27/11519 ,  H01L21/76202 ,  H01L27/11521 ,  H01L29/66825

    摘要： A method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. This method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird's beak encroachment and corner rounding effects usually found between neighboring cells due to inadequacies in the prior art photolithography process. This method and apparatus is particularly appropriate for use with EPROM, Flash EPROM, EEPROM, or other types of memory cells and in periphery devices.

    摘要翻译： 一种用于在半导体器件中使源区域与场氧化物区域和多晶硅栅极和字线自对准的方法和装置。 由于现有技术的光刻工艺中的不足之处，基本上消除了通常在相邻单元之间发现的鸟的喙侵入和拐角舍入效应，因此该方法和装置允许减小的存储单元尺寸和改进的器件密度。 该方法和装置特别适用于EPROM，闪存EPROM，EEPROM或其他类型的存储器单元和外围设备。