公开(公告)号：US06194784B1

公开(公告)日：2001-02-27

申请号：US08976969

申请日：1997-11-24

申请人： Krishna K. Parat ,  Glen N. Wada ,  Gregory E. Atwood ,  Daniel N. Tang

发明人： Krishna K. Parat ,  Glen N. Wada ,  Gregory E. Atwood ,  Daniel N. Tang

IPC分类号： H01L2348

CPC分类号： H01L27/11521 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： The encapsulation of gate stacks of a semiconductor device in an oxide insulative layer and in a silicon nitride etch-stop layer allows the formation of a contact filling for connection to underlying diffusion regions without risk of accidental diffusion contact to gate shorts created by the contact filling. As a result, the gate stacks may be patterned closer together, thus reducing the cell size and increasing the cell density. Furthermore, use of the etch-stop layer makes contact lithography easier since the size of the contact opening can be increased and contact alignment tolerance made less stringent without concern of increasing the cell size or of creating diffusion contact to gate shorts.

摘要翻译： 在氧化物绝缘层和氮化硅蚀刻停止层中封装半导体器件的栅极堆叠允许形成用于连接到下面的扩散区域的接触填充物，而不会发生与接触填充物产生的栅极短路的意外扩散接触的风险 。 结果，栅极堆叠可以被图案化在一起，从而减小电池尺寸并增加电池密度。 此外，使用蚀刻停止层使得接触光刻更容易，因为可以增加接触开口的尺寸并且接触对准公差变得不那么严格，而不考虑增加电池尺寸或产生与栅极短路的扩散接触。

公开(公告)号：US5229311A

公开(公告)日：1993-07-20

申请号：US859264

申请日：1992-03-25

申请人： Stefan K. Lai ,  Daniel N. Tang ,  Simon Y. Wang ,  Susan L. Kao ,  Baylor B. Triplett

发明人： Stefan K. Lai ,  Daniel N. Tang ,  Simon Y. Wang ,  Susan L. Kao ,  Baylor B. Triplett

IPC分类号： H01L23/532 ,  H01L29/45 ,  H01L29/788

CPC分类号： H01L23/53223 ,  H01L29/456 ,  H01L29/7881 ,  H01L2924/0002

摘要： A method of reducing the degradation effects associated with avalanche injection or tunnelling of hot-electrons in a field-effect semiconductor device is disclosed. The method of the present invention includes covering the active regions of the semiconductor device with a protective titanium barrier layer which is deposited directly underneath the ordinary metalization layers used for connecting the devices to bit and word lines within an array. Inclusion of the titanium barrier layer in a flash memory device results in a substantial improvement in the erasetime push-out and reduces excess charge loss normally associated with hot-electron devices.

摘要翻译： 公开了一种降低与场效应半导体器件中的热电子的雪崩注入或隧穿相关的劣化效应的方法。 本发明的方法包括用保护性钛阻挡层覆盖半导体器件的有源区，其直接沉积在用于将器件连接到阵列内的位和字线的普通金属化层的正下方。 将钛阻挡层包含在闪速存储器件中导致了时间推移的实质性改进，并且减少了与热电子器件通常相关的过量电荷损失。

公开(公告)号：US5103274A

公开(公告)日：1992-04-07

申请号：US672853

申请日：1991-03-20

申请人： Daniel N. Tang ,  Wen-Juei Lu

发明人： Daniel N. Tang ,  Wen-Juei Lu

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8247

CPC分类号： H01L27/11519 ,  H01L21/76202 ,  H01L27/11521 ,  H01L29/66825

摘要： A method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. This method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird's beak encroachment and corner rounding effects usually found between neighboring cells due to inadequacies in the prior art photolighography process.

摘要翻译： 一种用于在半导体器件中使源区域与场氧化物区域和多晶硅栅极和字线自对准的方法和装置。 该方法和装置通过基本上消除了由于现有技术的光引射过程中的不足而导致的相邻小区之间通常发现的鸟的喙侵入和拐角舍入效应而允许减小的存储单元尺寸和改进的器件密度。

公开(公告)号：US4806202A

公开(公告)日：1989-02-21

申请号：US104837

申请日：1987-10-05

申请人： Daniel N. Tang ,  Himanshu Choksi ,  Simon Wang ,  Simon M. Tam

发明人： Daniel N. Tang ,  Himanshu Choksi ,  Simon Wang ,  Simon M. Tam

IPC分类号： H01L21/316 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L21/312

CPC分类号： H01L21/28273 ,  Y10S148/058 ,  Y10S438/964

摘要： A method for growing tunnel oxides on a specially treated substrate surface. The method comprises steps for roughening the substrate surface to induce low tunneling voltage in the subsequently grown tunnel oxide layer. The tunnel oxide layer is grown in a low temperature steam cycle to further provide enhanced tunneling. The surface treatment comprises the steps of growing a first oxide layer to seal the surface of the substrate followed by growing a second oxide on the first oxide layer. In the preferred embodiment, a plasma etch utilizing an oxide etcher with high energy ion bombardment and an aluminum electrode is utilized to etch through the first and second oxide layers. The aluminum electrode causes sputtered aluminum on the second oxide layer's surface. The sputtered aluminum blocks the anisotropic etching leaving a grass type oxide residue on the substrate surface. The etching continues, overetching into the substrate surface. The grass type oxide residue causes pitting to occur on the substrate surface. This pitting, resulting in sharpened features on the surface, yields enhanced tunneling characteristics for a subsequently grown tunnel oxide layer. The residue is then removed and the surface cleaned. The tunnel oxide layer is grown in a low temperture steam cycle to preserve and enhance the sharp tips for the purpose of enhanced tunneling.

摘要翻译： 在特殊处理的基材表面上生长隧道氧化物的方法。 该方法包括用于使衬底表面粗糙化以在随后生长的隧道氧化物层中诱导低隧穿电压的步骤。 隧道氧化物层在低温蒸汽循环中生长以进一步提供增强的隧道。 表面处理包括生长第一氧化物层以密封衬底的表面，然后在第一氧化物层上生长第二氧化物的步骤。 在优选实施例中，利用利用具有高能离子轰击的氧化物蚀刻器和铝电极的等离子体蚀刻蚀刻穿过第一和第二氧化物层。 铝电极在第二氧化物层的表面上形成溅射的铝。 溅射的铝阻挡各向异性蚀刻，在基板表面上留下草型氧化物残留物。 蚀刻继续，过刻蚀进入衬底表面。 草型氧化物残留物在基材表面产生点蚀。 这种点蚀，导致在表面上锐化的特征，为随后生长的隧道氧化物层产生增强的隧穿特性。 然后将残余物除去并清洁表面。 隧道氧化物层在低温蒸汽循环中生长，以保护和增强锋利的尖端，以增强隧道的目的。

公开(公告)号：US5731242A

公开(公告)日：1998-03-24

申请号：US557904

申请日：1995-11-14

申请人： Krishna K. Parat ,  Glen N. Wada ,  Gregory E. Atwood ,  Daniel N. Tang

发明人： Krishna K. Parat ,  Glen N. Wada ,  Gregory E. Atwood ,  Daniel N. Tang

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/485 ,  H01L23/522 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82

CPC分类号： H01L27/11521 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L2924/0002

摘要： The encapsulation of gate stacks of a semiconductor device in an oxide insulative layer and in a silicon nitride etch-stop layer allows the formation of a contact filling for connection to underlying diffusion regions without risk of accidental diffusion contact to gate shorts created by the contact filling. As a result, the gate stacks may be patterned closer together, thus reducing the cell size and increasing the cell density. Furthermore, use of the etch-stop layer makes contact lithography easier since the size of the contact opening can be increased and contact alignment tolerance made less stringent without concern of increasing the cell size or of creating diffusion contact to gate shorts.

摘要翻译： 在氧化物绝缘层和氮化硅蚀刻停止层中封装半导体器件的栅极堆叠允许形成用于连接到下面的扩散区域的接触填充物，而不会发生意外扩散接触到由接触填充物产生的栅极短路的风险 。 结果，栅极堆叠可以被图案化在一起，从而减小电池尺寸并增加电池密度。 此外，使用蚀刻停止层使得接触光刻更容易，因为可以增加接触开口的尺寸并且接触对准公差变得不那么严格，而不考虑增加电池尺寸或产生与栅极短路的扩散接触。

公开(公告)号：US5466624A

公开(公告)日：1995-11-14

申请号：US315876

申请日：1994-09-30

申请人： Tong-Chern Ong ,  Daniel N. Tang

发明人： Tong-Chern Ong ,  Daniel N. Tang

IPC分类号： H01L21/762 ,  H01L21/8247 ,  H01L27/105

CPC分类号： H01L21/7621 ,  H01L21/76216 ,  H01L21/76221 ,  H01L27/105 ,  H01L27/11521

摘要： A method of forming a memory device with improved isolation between diffusion lines. Parallel, spaced apart thick oxide strips are grown on a substrate. Next, spaced apart, parallel strips having a polysilicon and nitride layer, oriented perpendicular to the first strips, are formed. The oxide between the second strips is removed, followed by an implantation to form source and drain regions. The nitride layer on the second strips is removed on those strips between two drain diffusions and an oxidation is performed to form self-aligned thick oxide over the source and drain regions. The strips from which the nitride has been removed are also oxidized, thus providing isolation between adjacent drain lines. In the formation of floating gate memory devices, a second polysilicon layer is deposited, and patterned in one direction to form strips overlying the second strips. After deposition of an intergate dielectric and a third polysilicon layer, a further patterning step is performed to form strips perpendicular to the second strips and second polysilicon layer and an etch is performed to etch the third polysilicon layer, intergate dielectric, second polysilicon layer and first polysilicon layer not covered by the patterning layer.

摘要翻译： 一种形成具有改善的扩散线隔离的存储器件的方法。 在衬底上生长平行的间隔开的厚氧化物条。 接下来，形成具有垂直于第一条带取向的多晶硅和氮化物层的间隔开的平行条。 去除第二条带之间的氧化物，随后进行注入以形成源区和漏区。 第二条带上的氮化物层在两个漏极扩散之间的那些条上被去除，并且进行氧化以在源极和漏极区域上形成自对准的厚氧化物。 去除氮化物的条带也被氧化，从而在相邻的排水管线之间提供隔离。 在浮栅存储器件的形成中，沉积第二多晶硅层，并在一个方向上图案化以形成覆盖第二条带的条带。 在沉积隔间电介质和第三多晶硅层之后，执行另外的图案化步骤以形成垂直于第二条带和第二多晶硅层的条带，并且执行蚀刻以蚀刻第三多晶硅层，隔间电介质，第二多晶硅层和第一多晶硅层 多晶硅层未被图形层覆盖。

公开(公告)号：US5190887A

公开(公告)日：1993-03-02

申请号：US815946

申请日：1991-12-30

申请人： Daniel N. Tang ,  Gregory E. Atwood

发明人： Daniel N. Tang ,  Gregory E. Atwood

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L29/66825 ,  H01L29/7835 ,  H01L29/7885

摘要： A method of forming a doped region within a monocrystalline silicon layer of an integrated circuit having an electrically erasable and electrically programmable memory device on a semiconductor substrate, wherein the doped region lies within a channel region near a drain region, but does not lie within a source region. After a patterned layer is formed over the channel region, the substrate is doped by ion implantation with a first dopant at a tilt angle no less than a minimum tilt angle and at about a predetermined azimuthal angle, such that a significant number of ions enter a drain region and a channel region near the drain region and substantially no ions enter a source region. The first dopant is the same dopant type as the monocrystalline silicon layer dopant. The drain region is masked. The source region is doped with a second dopant. The second dopant is an opposite dopant type as the monocrystalline silicon layer dopant. The source region and the drain region are doped with a third dopant. The third dopant is the same dopant type as the second dopant. The third dopant dose is heavier than the first dopant dose, and the second dopant diffusion coefficient is greater than the third dopant diffusion coefficient.

摘要翻译： 在半导体衬底上具有电可擦除和电可编程存储器件的集成电路的单晶硅层内形成掺杂区的方法，其中掺杂区位于漏区附近的沟道区内，但不在 源区。 在通道区域上形成图案层之后，通过离子注入掺杂衬底，以不小于最小倾斜角度和大约预定方位角的倾斜角以第一掺杂剂掺杂，使得大量离子进入 漏极区域和靠近漏极区域的沟道区域，并且基本上没有离子进入源极区域。 第一掺杂剂是与单晶硅层掺杂剂相同的掺杂剂类型。 漏极区域被掩蔽。 源区掺杂有第二掺杂剂。 第二掺杂剂是与单晶硅层掺杂剂相反的掺杂剂类型。 源极区和漏极区掺杂有第三掺杂剂。 第三掺杂剂是与第二掺杂剂相同的掺杂剂类型。 第三掺杂剂剂量比第一掺杂剂剂量重，第二掺杂剂扩散系数大于第三掺杂剂扩散系数。

公开(公告)号：US5120671A

公开(公告)日：1992-06-09

申请号：US621284

申请日：1990-11-29

申请人： Daniel N. Tang ,  Wen-Juei Lu

发明人： Daniel N. Tang ,  Wen-Juei Lu

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8247

CPC分类号： H01L27/11519 ,  H01L21/76202 ,  H01L27/11521 ,  H01L29/66825

摘要： A method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. This method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird's beak encroachment and corner rounding effects usually found between neighboring cells due to inadequacies in the prior art photolithography process. This method and apparatus is particularly appropriate for use with EPROM, Flash EPROM, EEPROM, or other types of memory cells and in periphery devices.

摘要翻译： 一种用于在半导体器件中使源区域与场氧化物区域和多晶硅栅极和字线自对准的方法和装置。 由于现有技术的光刻工艺中的不足之处，基本上消除了通常在相邻单元之间发现的鸟的喙侵入和拐角舍入效应，因此该方法和装置允许减小的存储单元尺寸和改进的器件密度。 该方法和装置特别适用于EPROM，闪存EPROM，EEPROM或其他类型的存储器单元和外围设备。