公开(公告)号：US06960803B2

公开(公告)日：2005-11-01

申请号：US10693067

申请日：2003-10-23

申请人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

发明人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L29/76

CPC分类号： H01L21/76895

摘要： A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

摘要翻译： 用作与半导体器件中的结构相邻的导电间隔件的接触件的接合焊盘包括两个岛，每个岛基本上为矩形并且彼此间隔开并且与该结构隔开。 导电间隔件与每个岛相邻并且彼此重叠并与邻近结构的导电间隔物重叠。 与着陆垫的接触在邻近岛的导电间隔物上并且与结构间隔开。

公开(公告)号：US07358559B2

公开(公告)日：2008-04-15

申请号：US11239791

申请日：2005-09-29

申请人： Felix (Ying-Kit) Tsui ,  Jeng-Wei Yang ,  Bomy Chen ,  Chun-Ming Chen ,  Dana Lee ,  Changyuan Chen

发明人： Felix (Ying-Kit) Tsui ,  Jeng-Wei Yang ,  Bomy Chen ,  Chun-Ming Chen ,  Dana Lee ,  Changyuan Chen

IPC分类号： H01L29/788

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336

摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. An array of such memory cells comprises rows of cells in active regions adjacent to one another separated from one another by the semiconductive substrate material without any isolation material. Cells in the same column have the source/drain region in common, the drain/source region in common and a first and second control gates in each of the trenches in common. Cells in adjacent columns have the source/drain in common and the first control gate in common.

摘要翻译： 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 控制栅极连接到每个源极/漏极区域，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。 这种存储单元的阵列包括彼此相邻的活性区域中的细胞排，所述活性区域通过没有任何隔离材料的半导体衬底材料彼此分开。 相同列中的单元具有共同的源极/漏极区域，共同的漏极/源极区域以及每个沟槽中的第一和第二控制栅极共同。 相邻列中的单元具有共同的源极/漏极，第一个控制栅极共同。

公开(公告)号：US07749779B2

公开(公告)日：2010-07-06

申请号：US12266443

申请日：2008-11-06

申请人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

发明人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

IPC分类号： H01L21/66

CPC分类号： H01L21/76895

摘要： A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

摘要翻译： 用作与半导体器件中的结构相邻的导电间隔件的接触件的接合焊盘包括两个岛，每个岛基本上为矩形并且彼此间隔开并且与该结构隔开。 导电间隔件与每个岛相邻并且彼此重叠并与邻近结构的导电间隔物重叠。 与着陆垫的接触在邻近岛的导电间隔物上并且与结构间隔开。

公开(公告)号：US08848428B2

公开(公告)日：2014-09-30

申请号：US13548421

申请日：2012-07-13

申请人： Hau-Yan Lu ,  Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

发明人： Hau-Yan Lu ,  Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC分类号： G11C11/24 ,  H01L27/108 ,  G11C7/00 ,  G11C29/00 ,  H01L29/24

CPC分类号： G11C8/14 ,  G11C11/408 ,  G11C11/4097

摘要： One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline.

摘要翻译： 一个实施例涉及一种包括多个存储单元的存储器件，该多个存储器单元被拼凑在一起以形成存储器阵列。 存储单元包括多个存储单元，其包括设置在半导体衬底上的各自的电容器和相应的晶体管。 电容器包括设置在半导体衬底中的导电区域中的相应的下板。 字线在导电区域上延伸，并且接触将字线连接到导电区域，以将字线耦合到相应电容器的下板。 相应的晶体管被​​布置成使得晶体管的连续栅极被布置在字线的交替侧上。

公开(公告)号：US20140016399A1

公开(公告)日：2014-01-16

申请号：US13548421

申请日：2012-07-13

申请人： Hau-Yan Lu ,  Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

发明人： Hau-Yan Lu ,  Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC分类号： G11C11/24

CPC分类号： G11C8/14 ,  G11C11/408 ,  G11C11/4097

摘要： One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline.

摘要翻译： 一个实施例涉及一种包括多个存储单元的存储器件，该多个存储器单元被拼凑在一起以形成存储器阵列。 存储单元包括多个存储单元，其包括设置在半导体衬底上的各自的电容器和相应的晶体管。 电容器包括设置在半导体衬底中的导电区域中的相应的下板。 字线在导电区域上延伸，并且接触将字线连接到导电区域，以将字线耦合到相应电容器的下板。 相应的晶体管被​​布置成使得晶体管的连续栅极被布置在字线的交替侧上。

公开(公告)号：US20090061547A1

公开(公告)日：2009-03-05

申请号：US12266443

申请日：2008-11-06

申请人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

发明人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

IPC分类号： H01L21/66

CPC分类号： H01L21/76895

摘要： A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

摘要翻译： 用作与半导体器件中的结构相邻的导电间隔件的接触件的接合焊盘包括两个岛，每个岛基本上为矩形并且彼此间隔开并且与该结构隔开。 导电间隔件与每个岛相邻并且彼此重叠并与邻近结构的导电间隔物重叠。 与着陆垫的接触在邻近岛的导电间隔物上并且与结构间隔开。

公开(公告)号：US07470949B1

公开(公告)日：2008-12-30

申请号：US11828213

申请日：2007-07-25

申请人： Bomy Chen ,  Yuniarto Widjaja ,  Jack Edward Frayer ,  Felix (Ying-Kit) Tsui

发明人： Bomy Chen ,  Yuniarto Widjaja ,  Jack Edward Frayer ,  Felix (Ying-Kit) Tsui

IPC分类号： H01L27/108

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

摘要： A nonvolatile memory cell has a charge trapping layer for the storage of charges thereon. The cell is a bidirectional cell in a substrate of a first conductivity. The cell has two spaced apart trenches. Within each trench, at the bottom thereof is a region of a second conductivity. A channel extends from one of the region at the bottom of one of the trenches along the side wall of that trench to the top planar surface of the substrate, and along the sidewall of the adjacent trench to the region at the bottom of the adjacent trench. The trapping layer is along the sidewall of each of the two trenches. A control gate is in each of the trenches capacitively coupled to the trapping layer along the sidewall and to the region at the bottom of the trench. Each of the trenches can stored a plurality of bits.

摘要翻译： 非易失性存储单元具有用于在其上存储电荷的电荷捕获层。 电池是第一导电性衬底中的双向电池。 电池具有两个间隔开的沟槽。 在每个沟槽内，其底部是第二导电性的区域。 一个通道从一个沟槽底部的一个区域沿着该沟槽的侧壁延伸到衬底的顶部平坦表面，并且沿相邻沟槽的侧壁延伸到相邻沟槽底部的区域 。 捕获层沿着两个沟槽中的每一个的侧壁。 控制栅极位于每个沟槽中，每个沟槽沿着侧壁电容耦合到捕获层，并且在沟槽的底部与区域电容耦合。 每个沟槽可以存储多个位。