公开(公告)号：US08400337B1

公开(公告)日：2013-03-19

申请号：US12987893

申请日：2011-01-10

Applicant: Danfeng Xu ,  Jenn-Gang Chern

Inventor： Danfeng Xu ,  Jenn-Gang Chern

IPC: H03M1/06 ,  H03K3/011

CPC classification number: H03F3/45183 ,  H03F3/45766 ,  H03F2203/45048 ,  H03F2203/45291 ,  H03F2203/45342 ,  H03F2203/45354 ,  H03M1/1019

Abstract: Offset is canceled by determining a voltage level to set a body input of a transistor to. The body input of the transistor is set to the determined voltage level to cancel offset associated with the transistor.

Abstract translation: 通过确定将晶体管的体输入设置为的电压电平来消除偏移。 将晶体管的体输入设置为确定的电压电平以消除与晶体管相关联的偏移。

公开(公告)号：US20060093028A1

公开(公告)日：2006-05-04

申请号：US10978755

申请日：2004-11-01

Applicant: Vishnu Balan ,  Joseph Caroselli ,  Ye Liu ,  Chintan Desai ,  Jenn-Gang Chern

Inventor： Vishnu Balan ,  Joseph Caroselli ,  Ye Liu ,  Chintan Desai ,  Jenn-Gang Chern

IPC: H03H7/30

CPC classification number: H04L25/03343 ,  H04L2025/0349

Abstract: A multi-phase adaptive decision feedback equalizer minimizes post-cursor inter-symbol interference in a current data bit based on values of subsequent data bits in a data communication system. In one form, the receiver includes a plurality of modules each having a respective adaptive decision feedback equalizer. A processor responsive to output signals from each of the plurality of modules generates a plurality of coefficient values. The adaptive decision feedback equalizer has a plurality of taps receiving a respective output signal from one of the modules and a respective coefficient value to generate a respective correction signal. The correction signals are summed with the data signal and processed to recover the data. Pre-calculation of coefficients permits rapid selection of data. Multi-phase operation permits higher data frequencies.

Abstract translation: 多相自适应判决反馈均衡器基于数据通信系统中的后续数据位的值来最小化当前数据位中的后标记符号间干扰。 在一种形式中，接收机包括多个模块，每个模块具有相应的自适应判决反馈均衡器。 响应于来自多个模块中的每一个的输出信号的处理器产生多个系数值。 自适应判决反馈均衡器具有接收来自模块之一的相应输出信号的多个抽头和相应的系数值以产生相应的校正信号。 校正信号与数据信号相加并被处理以恢复数据。 系数的预先计算允许快速选择数据。 多相操作允许更高的数据频率。

公开(公告)号：US07440497B2

公开(公告)日：2008-10-21

申请号：US10978755

申请日：2004-11-01

Applicant: Vishnu Balan ,  Joseph Caroselli, Jr. ,  Ye Liu ,  Chintan M. Desai ,  Jenn-Gang Chern

Inventor： Vishnu Balan ,  Joseph Caroselli, Jr. ,  Ye Liu ,  Chintan M. Desai ,  Jenn-Gang Chern

IPC: H03H7/03

CPC classification number: H04L25/03343 ,  H04L2025/0349

Abstract: A multi-phase adaptive decision feedback equalizer minimizes post-cursor inter-symbol interference in a current data bit based on values of subsequent data bits in a data communication system. In one form, the receiver includes a plurality of modules each having a respective adaptive decision feedback equalizer. A processor responsive to output signals from each of the plurality of modules generates a plurality of coefficient values. The adaptive decision feedback equalizer has a plurality of taps receiving a respective output signal from one of the modules and a respective coefficient value to generate a respective correction signal. The correction signals are summed with the data signal and processed to recover the data. Pre-calculation of coefficients permits rapid selection of data. Multi-phase operation permits higher data frequencies.

Abstract translation: 多相自适应判决反馈均衡器基于数据通信系统中的后续数据位的值来最小化当前数据位中的后标记符号间干扰。 在一种形式中，接收机包括多个模块，每个模块具有相应的自适应判决反馈均衡器。 响应于来自多个模块中的每一个的输出信号的处理器产生多个系数值。 自适应判决反馈均衡器具有接收来自模块之一的相应输出信号的多个抽头和相应的系数值以产生相应的校正信号。 校正信号与数据信号相加并被处理以恢复数据。 系数的预先计算允许快速选择数据。 多相操作允许更高的数据频率。

公开(公告)号：US06236257B1

公开(公告)日：2001-05-22

申请号：US09164867

申请日：1998-10-01

Applicant: Xiaomin Si ,  Jenn-Gang Chern

Inventor： Xiaomin Si ,  Jenn-Gang Chern

IPC: H03K1716

CPC classification number: H03K19/00353

Abstract: An emitter follower circuit with feed forward compensation includes an emitter follower having an emitter follower input and an emitter follower output. An auxiliary emitter follower has an auxiliary emitter follower input and an auxiliary emitter follower output. The emitter follower input is coupled to the auxiliary emitter follower input and the emitter follower output is capacitively coupled to the auxiliary emitter follower output. In this manner, ringing of the emitter follower circuit with feed forward compensation is reduced by the capacitive coupling of the auxiliary emitter follower output to the emitter follower output.

Abstract translation: 具有前馈补偿的射极跟随器电路包括具有射极跟随器输入和射极跟随器输出的射极跟随器。 辅助射极跟随器具有辅助射极跟随器输入和辅助射极跟随器输出。 射极跟随器输入耦合到辅助射极跟随器输入，射极跟随器输出电容耦合到辅助射极跟随器输出端。 以这种方式，通过辅助射极跟随器输出到射极跟随器输出的电容耦合，减少了具有前馈补偿的射极跟随器电路的振荡。

公开(公告)号：US5351015A

公开(公告)日：1994-09-27

申请号：US12914

申请日：1993-02-03

Applicant: Rodney T. Masumoto ,  Shunsaku Ueda ,  Jenn-Gang Chern ,  Kirby Lam

Inventor： Rodney T. Masumoto ,  Shunsaku Ueda ,  Jenn-Gang Chern ,  Kirby Lam

IPC: G11B20/12 ,  G11B20/14 ,  H03L3/00 ,  H03L7/089 ,  H03L7/189 ,  H03L7/00

CPC classification number: G11B20/1403 ,  H03L3/00 ,  H03L7/0891 ,  H03L7/189 ,  G11B20/1258 ,  H03L2207/06

Abstract: The present invention provides a method and an apparatus for controlling initial transients in a frequency synthesizer by controlling the start-up sequence of the device. The start-up sequence comprises several steps. The voltage controlled oscillator(s) (VCO) is reset so that the VCO(s) are in a known state during start-up. The charge pump and phase detector of phase-locked loop (PLL) are disabled. New data values are loaded into counter(s)/register(s) that control the frequency of the VCO(s). Also, a data value is provided to a digital-to-analog converter (DAC) to set the data rate for the PLL. A fixed amount of time is provided as a delay for the DAC to settle (i.e., 1.6 .mu.s). Divide-by-M and divide-by-N counters are then enabled. Also, the phase detector of the phase-locked loop (PLL) is enabled. The VCO is then restarted. By utilizing a start-up sequence, the center frequency of the VCO is already settled when changing frequencies, the divide-by-M and divide-by-N counters are matched, the VCO starts in phase with the reference frequency of the reference signal, and the voltage of the loop filter is prevented from railing. By using dual buffered registers for each counter, loading of the divide-by-M and divide-by-N counters is accomplished without shutting down the VCO. A timer provides a 1.6 .mu.s delay to allow the DAC to settle. Digital logic is used to synchronize signals. Delay compensation circuitry is used to implement delay cancellation for zero phase restart.

Abstract translation: 本发明提供一种通过控制装置启动顺序来控制频率合成器中的初始瞬变的方法和装置。 启动顺序包括几个步骤。 压控振荡器（VCO）被复位，使得VCO在启动期间处于已知状态。 锁相环（PLL）的电荷泵和相位检测器被禁用。 新的数据值被加载到控制VCO频率的计数器/寄存器中。 另外，将数据值提供给数模转换器（DAC）以设置PLL的数据速率。 提供固定的时间量作为DAC稳定的延迟（即1.6μs）。 然后启用除以M和N分频计数器。 此外，锁相环（PLL）的相位检测器使能。 然后重新启动VCO。 通过利用启动序列，VCO的中心频率在改变频率时已经稳定，除以M和除以N的计数器相匹配，VCO与参考信号的参考频率同相启动 ，并且防止环路滤波器的电压进行栏杆。 通过对每个计数器使用双缓冲寄存器，可以在不关闭VCO的情况下完成M分频和N分频计数器的加载。 一个定时器提供1.6μs的延迟以允许DAC稳定。 数字逻辑用于同步信号。 延迟补偿电路用于实现零相重启的延迟消除。

公开(公告)号：US20110115659A1

公开(公告)日：2011-05-19

申请号：US12939965

申请日：2010-11-04

Applicant: Jenn-Gang Chern

Inventor： Jenn-Gang Chern

IPC: H03M1/06

CPC classification number: H03M1/1019 ,  H03M1/365

Abstract: An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset.

Abstract translation: 公开了使用数模转换器（DAC）的偏移补偿方案。 在一些实施例中，DAC耦合到具有不期望的电流或电压偏移的电路，并且被配置为至少部分地补偿不期望的电流或电压偏移。 例如，在一些实施例中，DAC将电流或电压注入到电路中，该电流或电压将电路的电流或电压移动量大小相等或相似，极性相反于电路的电流或电压的偏移， 不需要的电流或电压偏移。

公开(公告)号：US07528752B1

公开(公告)日：2009-05-05

申请号：US11787141

申请日：2007-04-13

Applicant: Jenn-Gang Chern

Inventor： Jenn-Gang Chern

IPC: H03M1/06

CPC classification number: H03M1/1019 ,  H03M1/365

Abstract: An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset.

Abstract translation: 公开了使用数模转换器（DAC）的偏移补偿方案。 在一些实施例中，DAC耦合到具有不期望的电流或电压偏移的电路，并且被配置为至少部分地补偿不期望的电流或电压偏移。 例如，在一些实施例中，DAC将电流或电压注入到电路中，该电流或电压将电路的电流或电压移动量大小相等或相似，极性相反于电路的电流或电压的偏移， 不需要的电流或电压偏移。

公开(公告)号：US08350736B2

公开(公告)日：2013-01-08

申请号：US12939965

申请日：2010-11-04

Applicant: Jenn-Gang Chern

Inventor： Jenn-Gang Chern

IPC: H03M1/06

CPC classification number: H03M1/1019 ,  H03M1/365

Abstract: An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset.

公开(公告)号：US20100019943A1

公开(公告)日：2010-01-28

申请号：US12383259

申请日：2009-03-19

Applicant: Jenn-Gang Chern

Inventor： Jenn-Gang Chern

IPC: H03M1/06 ,  H03M1/10

CPC classification number: H03M1/1019 ,  H03M1/365

Abstract: An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset.

Abstract translation: 公开了使用数模转换器（DAC）的偏移补偿方案。 在一些实施例中，DAC耦合到具有不期望的电流或电压偏移的电路，并且被配置为至少部分地补偿不期望的电流或电压偏移。 例如，在一些实施例中，DAC将电流或电压注入到电路中，该电流或电压将电路的电流或电压移动量大小相等或相似，极性相反于电路的电流或电压的偏移， 不需要的电流或电压偏移。

公开(公告)号：US5796358A

公开(公告)日：1998-08-18

申请号：US693587

申请日：1996-08-01

Applicant: Shih-Ming Shih ,  James Wilson Rae ,  Richard A. Contreras ,  Jenn-Gang Chern

Inventor： Shih-Ming Shih ,  James Wilson Rae ,  Richard A. Contreras ,  Jenn-Gang Chern

IPC: H03M1/18 ,  H03M1/00

CPC classification number: H03M1/183

Abstract: Analog-to-digital (ADC) output bits are partitioned in a way that simplifies the gain error calculations. Simplification of the gain error calculations allows a reduction in the complexity of the circuits needed to implement automatic gain control (AGC).

Abstract translation: 模数（ADC）输出位以简化增益误差计算的方式进行分区。 增益误差计算的简化可以降低实现自动增益控制（AGC）所需电路的复杂度。