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公开(公告)号：US07774519B2
公开(公告)日：2010-08-10
申请号：US12167298
申请日：2008-07-03
CPC分类号： G06F13/12
摘要： A bi-directional and full duplex facility for permitting both the IO processor and the Channel to write CCA messages on their respective queues at the same time. IOP messages to the channel are stored on the TO_CHN queue and Channel messages to the IOP on the TO_IOP queue. CCA Queues replace hardware CCAs due to increasing transmission capabilities of current IO processors and Channel processors. Even though the mechanism is similar, the present invention provides some benefits in the use of signaling. The IOP does not have to signal the Channel each time it puts something on its outbound queue. Each queue contains multiple slots. This allows the IOP and Channel to write multiple messages on the targeted queue without encountering a CCA busy signal. The actual queues are now structured in hardware system memory.
摘要翻译： 双向和全双工设备，用于允许IO处理器和通道同时在其各自的队列上写入CCA消息。 到该通道的IOP消息存储在TO_CHN队列上，并将通道消息存储到TO_IOP队列上的IOP。 由于当前IO处理器和通道处理器的传输能力不断增加，CCA队列取代硬件CCA。 即使该机制相似，本发明在使用信令方面提供了一些益处。 每当它在其出站队列上放置某些东西时，IOP都不必向Channel发出信号。 每个队列包含多个插槽。 这允许IOP和Channel在目标队列上写入多个消息，而不会遇到CCA忙信号。 实际的队列现在由硬件系统内存构成。
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公开(公告)号：US20090037618A1
公开(公告)日：2009-02-05
申请号：US12167298
申请日：2008-07-03
IPC分类号： G06F13/00
CPC分类号： G06F13/12
摘要： A bi-directional and full duplex facility for permitting both the IO processor and the Channel to write CCA messages on their respective queues at the same time. IOP messages to the channel are stored on the TO_CHN queue and Channel messages to the IOP on the TO_IOP queue. CCA Queues replace hardware CCAs due to increasing transmission capabilities of current IO processors and Channel processors. Even though the mechanism is similar, the present invention provides some benefits in the use of signaling. The IOP does not have to signal the Channel each time it puts something on its outbound queue. Each queue contains multiple slots. This allows the IOP and Channel to write multiple messages on the targeted queue without encountering a CCA busy signal. The actual queues are now structured in hardware system memory.
摘要翻译： 双向和全双工设备，用于允许IO处理器和通道同时在其各自的队列上写入CCA消息。 到该通道的IOP消息存储在TO_CHN队列上，并将通道消息存储到TO_IOP队列上的IOP。 由于当前IO处理器和通道处理器的传输能力不断增加，CCA队列取代硬件CCA。 即使该机制相似，本发明在使用信令方面提供了一些益处。 每当它在其出站队列上放置某些东西时，IOP都不必向Channel发出信号。 每个队列包含多个插槽。 这允许IOP和Channel在目标队列上写入多个消息，而不会遇到CCA忙信号。 实际的队列现在由硬件系统内存构成。
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公开(公告)号：US07437490B2
公开(公告)日：2008-10-14
申请号：US11139728
申请日：2005-05-27
CPC分类号： G06F13/12
摘要： A bi-directional and full duplex facility for permitting both the IO processor and the Channel to write CCA messages on their respective queues at the same time. IOP messages to the channel are stored on the TO_CHN queue and Channel messages to the IOP on the TO_IOP queue. CCA Queues replace hardware CCAs due to increasing transmission capabilities of current IO processors and Channel processors. Even though the mechanism is similar, the present invention provides some benefits in the use of signaling. The IOP does not have to signal the Channel each time it puts something on its outbound queue. Each queue contains multiple slots. This allows the IOP and Channel to write multiple messages on the targeted queue without encountering a CCA busy signal. The actual queues are now structured in hardware system memory.
摘要翻译： 双向和全双工设备，用于允许IO处理器和通道同时在其各自的队列上写入CCA消息。 到该通道的IOP消息存储在TO_CHN队列上，并将通道消息存储到TO_IOP队列上的IOP。 由于当前IO处理器和通道处理器的传输能力不断增加，CCA队列取代硬件CCA。 即使该机制相似，本发明在使用信令方面提供了一些益处。 每当它在其出站队列上放置某些东西时，IOP都不必向Channel发出信号。 每个队列包含多个插槽。 这允许IOP和Channel在目标队列上写入多个消息，而不会遇到CCA忙信号。 实际的队列现在由硬件系统内存构成。
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公开(公告)号：US20130339551A1
公开(公告)日：2013-12-19
申请号：US13523958
申请日：2012-06-15
申请人： John R. Flanagan , Francis Gassert , Kenneth J. Oakes , Dale F. Riedy , Peter Sutton , John S. Trotter , Harry M. Yudenfriend
发明人： John R. Flanagan , Francis Gassert , Kenneth J. Oakes , Dale F. Riedy , Peter Sutton , John S. Trotter , Harry M. Yudenfriend
IPC分类号： G06F3/00
CPC分类号： G06F13/4022
摘要： A computer system includes a processor configured for detecting initial command response times of a plurality of paths for transmitting signals from the processor to one or more external devices via a plurality of channels, assigning weighted values to the plurality of paths based on the detected initial command response times, and modifying a frequency at which respective paths among the plurality of paths are selected for transmitting the signals based on the weighted values assigned to the respective paths.
摘要翻译： 计算机系统包括：处理器，被配置为检测多个路径的初始命令响应时间，用于经由多个信道将信号从处理器发送到一个或多个外部设备;基于检测到的初始命令向多个路径分配加权值 响应时间，以及修改多个路径中的相应路径被选择用于基于分配给相应路径的加权值来发送信号的频率。
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公开(公告)号：US08812742B2
公开(公告)日：2014-08-19
申请号：US13523958
申请日：2012-06-15
申请人： John R. Flanagan , Francis Gassert , Kenneth J. Oakes , Dale F. Riedy , Peter G. Sutton , John Trotter , Harry M. Yudenfriend
发明人： John R. Flanagan , Francis Gassert , Kenneth J. Oakes , Dale F. Riedy , Peter G. Sutton , John Trotter , Harry M. Yudenfriend
CPC分类号： G06F13/4022
摘要： A computer system includes a processor configured for detecting initial command response times of a plurality of paths for transmitting signals from the processor to one or more external devices via a plurality of channels, assigning weighted values to the plurality of paths based on the detected initial command response times, and modifying a frequency at which respective paths among the plurality of paths are selected for transmitting the signals based on the weighted values assigned to the respective paths.
摘要翻译： 计算机系统包括：处理器，被配置为检测多个路径的初始命令响应时间，用于经由多个信道将信号从处理器发送到一个或多个外部设备;基于检测到的初始命令向多个路径分配加权值 响应时间，以及修改多个路径中的相应路径被选择用于基于分配给相应路径的加权值来发送信号的频率。
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公开(公告)号：US06687853B1
公开(公告)日：2004-02-03
申请号：US09583670
申请日：2000-05-31
申请人： Patricia G. Driever , John R. Flanagan , Paul S. Frazer , Catherine C. Huang , Bernhard Laubli , Louis W. Ricci
发明人： Patricia G. Driever , John R. Flanagan , Paul S. Frazer , Catherine C. Huang , Bernhard Laubli , Louis W. Ricci
IPC分类号： G06F1100
CPC分类号： G06F11/1443
摘要： A method, program product and apparatus for checkpointing for recovery of channels in a data processing system using a protocol which allows for multiplexing operations at the frame level and streaming of commands and data. For unsuccessful retries, the correct primary CCW address is reported back to software indicating the extent to which the channel completed modifying and accessing S/390 storage.
摘要翻译： 一种使用允许在帧级复用操作和命令和数据流的协议的数据处理系统中的信道恢复检查点的方法，程序产品和装置。 对于不成功的重试，将正确的主CCW地址报告回软件，指示通道完成修改和访问S / 390存储的程度。
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公开(公告)号：US09052837B2
公开(公告)日：2015-06-09
申请号：US12031182
申请日：2008-02-14
申请人： Catherine C. Huang , Daniel F. Casper , John R. Flanagan , Roger G. Hathorn , Matthew J. Kalos , Louis W. Rcci
发明人： Catherine C. Huang , Daniel F. Casper , John R. Flanagan , Roger G. Hathorn , Matthew J. Kalos , Louis W. Rcci
CPC分类号： G06F13/4027 , G06F3/0607 , G06F3/0619 , G06F3/0659 , G06F3/0661 , G06F3/0689 , G06F13/28
摘要： Articles of manufacture, apparatuses, and methods for processing communications between a control unit and a channel subsystem in an input/output processing system are disclosed. Embodiments of the invention include an article of manufacture including at least one computer usable medium having computer readable program code logic to processing communications between a control unit and a channel subsystem in an input/output processing system. The computer readable program code logic performs a method including: sending a message in a first mode from the control unit to the channel subsystem; receiving a command in a second mode from the channel subsystem at the control unit; determining whether the command is responsive to the message; and responsive to the command being not responsive to the message, determining whether to perform one of i) executing the command and ii) terminating the command.
摘要翻译： 公开了用于在输入/输出处理系统中处理控制单元和通道子系统之间的通信的制造，设备和方法。 本发明的实施例包括一种制品，其包括具有计算机可读程序代码逻辑的至少一个计算机可用介质，以在输入/输出处理系统中处理控制单元和通道子系统之间的通信。 计算机可读程序代码逻辑执行一种方法，包括：以第一模式从控制单元向通道子系统发送消息; 在所述控制单元处从所述通道子系统接收第二模式的命令; 确定所述命令是否响应于所述消息; 并且响应于所述命令不响应所述消息，确定是否执行i）执行所述命令和ii）终止所述命令之一。
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公开(公告)号：US08677027B2
公开(公告)日：2014-03-18
申请号：US13150545
申请日：2011-06-01
CPC分类号： G06F13/385
摘要： A computer program product for performing input/output (I/O) processing is configured for performing a method including: obtaining information relating to an I/O operation at a channel subsystem; generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a field for storing header information; generating an address control structure specifying a location in the local channel memory of a corresponding ACW; receiving a data transfer request from a network interface that includes the address control structure; responsive to an input data request, routing the data to at least one host memory location specified by the corresponding ACW and storing header information in the corresponding ACW; and responsive to an output data request, routing the data from a host memory location specified by the ACW to the network interface and appending header information to the data.
摘要翻译： 用于执行输入/输出（I / O）处理的计算机程序产品被配置为执行一种方法，包括：获得与通道子系统上的I / O操作有关的信息; 在本地信道存储器中生成和存储指定用于数据传输的一个或多个主机存储器位置的至少一个地址控制字（ACW），并且包括用于存储头信息的字段; 产生指定相应ACW的本地信道存储器中的位置的地址控制结构; 从包括所述地址控制结构的网络接口接收数据传输请求; 响应于输入数据请求，将数据路由到由相应ACW指定的至少一个主机存储器位置，并将标题信息存储在相应的ACW中; 并且响应于输出数据请求，将数据从由ACW指定的主机存储器位置路由到网络接口，并将标题信息附加到数据。
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公开(公告)号：US08583988B2
公开(公告)日：2013-11-12
申请号：US13150549
申请日：2011-06-01
CPC分类号： G06F13/387
摘要： A computer program product for performing input/output (I/O) processing is provided. The computer program product is configured to perform: obtaining information relating to an I/O operation at a channel subsystem; generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data check word generation field and/or a data check word save field; responsive to receiving an input data transfer request including at least one data check word, storing the at least one data check word in the data check word save field and performing a check of the data to determine whether the data has been corrupted; and responsive to receiving an output data transfer, generating at least one data check word based on the data check word generation field and appending the at least one data check word to the data.
摘要翻译： 提供了用于执行输入/输出（I / O）处理的计算机程序产品。 计算机程序产品被配置为执行：获得与通道子系统上的I / O操作有关的信息; 在本地信道存储器中生成和存储指定用于数据传输的一个或多个主机存储器位置的至少一个地址控制字（ACW），并且包括数据检查词生成字段和/或数据检查字保存字段; 响应于接收到包括至少一个数据检查字的输入数据传输请求，将所述至少一个数据检查词存储在数据检查字保存字段中，并且执行数据检查以确定数据是否已被破坏; 并且响应于接收到输出数据传输，基于所述数据检查词生成字段生成至少一个数据检查字，并将所述至少一个数据检查词附加到所述数据。
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公开(公告)号：US08364854B2
公开(公告)日：2013-01-29
申请号：US13150555
申请日：2011-06-01
IPC分类号： G06F3/00 , G06F15/16 , G06F15/173 , H03M13/00
CPC分类号： G06F13/12 , G06F13/16 , G06F13/20 , G06F13/42 , G06F13/4221
摘要： A computer program product is provided for performing input/output (I/O) processing at a host computer system. The computer program product is configured to perform: generating an address control structure for each of a plurality of consecutive data transfer requests specified by an I/O operation, each address control structure specifying a location in the local channel memory of a corresponding address control word (ACW) that includes an Offset field indicating a relative order of a data transfer request; generating and storing in local channel memory at least one ACW specifying one or more host memory locations for the plurality of consecutive data transfer requests and including an Expected Offset field indicating a relative order of an expected data transfer request; receiving a transfer request from the network interface and comparing the Offset field and the Expected Offset field to determine whether the data transfer request has been received in the correct order.
摘要翻译： 提供了一种用于在主计算机系统上执行输入/输出（I / O）处理的计算机程序产品。 计算机程序产品被配置为执行：为由I / O操作指定的多个连续数据传送请求中的每一个生成地址控制结构，每个地址控制结构指定本地信道存储器中对应地址控制字的位置 （ACW），其包括指示数据传送请求的相对顺序的偏移字段; 在本地信道存储器中生成和存储至少一个ACW，其指定用于所述多个连续数据传输请求的一个或多个主机存储器位置，并且包括指示预期数据传送请求的相对顺序的预期偏移字段; 从网络接口接收传输请求，并比较偏移字段和预期偏移字段，以确定数据传输请求是否以正确的顺序被接收。
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