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    Channel communication array queues in hardware system area
    1.
    发明授权
    Channel communication array queues in hardware system area 有权
    硬件系统区域中的通道通信阵列队列

    公开(公告)号：US07774519B2

    公开(公告)日：2010-08-10

    申请号：US12167298

    申请日：2008-07-03

    申请人： Daniel F. Casper ,  John R. Flanagan ,  Paul S. Frazer ,  Kenneth J. Oakes ,  John S. Trotter

    发明人： Daniel F. Casper ,  John R. Flanagan ,  Paul S. Frazer ,  Kenneth J. Oakes ,  John S. Trotter

    IPC分类号： G06F3/00 ,  G06F13/12

    CPC分类号： G06F13/12

    摘要： A bi-directional and full duplex facility for permitting both the IO processor and the Channel to write CCA messages on their respective queues at the same time. IOP messages to the channel are stored on the TO_CHN queue and Channel messages to the IOP on the TO_IOP queue. CCA Queues replace hardware CCAs due to increasing transmission capabilities of current IO processors and Channel processors. Even though the mechanism is similar, the present invention provides some benefits in the use of signaling. The IOP does not have to signal the Channel each time it puts something on its outbound queue. Each queue contains multiple slots. This allows the IOP and Channel to write multiple messages on the targeted queue without encountering a CCA busy signal. The actual queues are now structured in hardware system memory.

    摘要翻译： 双向和全双工设备，用于允许IO处理器和通道同时在其各自的队列上写入CCA消息。 到该通道的IOP消息存储在TO_CHN队列上，并将通道消息存储到TO_IOP队列上的IOP。 由于当前IO处理器和通道处理器的传输能力不断增加，CCA队列取代硬件CCA。 即使该机制相似，本发明在使用信令方面提供了一些益处。 每当它在其出站队列上放置某些东西时，IOP都不必向Channel发出信号。 每个队列包含多个插槽。 这允许IOP和Channel在目标队列上写入多个消息，而不会遇到CCA忙信号。 实际的队列现在由硬件系统内存构成。

    Channel communicaton Array Queues in Hardware System Area
    2.
    发明申请
    Channel communicaton Array Queues in Hardware System Area 有权
    硬件系统领域的通道通信阵列队列

    公开(公告)号：US20090037618A1

    公开(公告)日：2009-02-05

    申请号：US12167298

    申请日：2008-07-03

    申请人： Daniel F Casper ,  John R. Flanagan ,  Paul S. Frazer ,  Kenneth J. Oakes ,  John S. Trotter

    发明人： Daniel F Casper ,  John R. Flanagan ,  Paul S. Frazer ,  Kenneth J. Oakes ,  John S. Trotter

    IPC分类号： G06F13/00

    CPC分类号： G06F13/12

    摘要： A bi-directional and full duplex facility for permitting both the IO processor and the Channel to write CCA messages on their respective queues at the same time. IOP messages to the channel are stored on the TO_CHN queue and Channel messages to the IOP on the TO_IOP queue. CCA Queues replace hardware CCAs due to increasing transmission capabilities of current IO processors and Channel processors. Even though the mechanism is similar, the present invention provides some benefits in the use of signaling. The IOP does not have to signal the Channel each time it puts something on its outbound queue. Each queue contains multiple slots. This allows the IOP and Channel to write multiple messages on the targeted queue without encountering a CCA busy signal. The actual queues are now structured in hardware system memory.

    摘要翻译： 双向和全双工设备，用于允许IO处理器和通道同时在其各自的队列上写入CCA消息。 到该通道的IOP消息存储在TO_CHN队列上，并将通道消息存储到TO_IOP队列上的IOP。 由于当前IO处理器和通道处理器的传输能力不断增加，CCA队列取代硬件CCA。 即使该机制相似，本发明在使用信令方面提供了一些益处。 每当它在其出站队列上放置某些东西时，IOP都不必向Channel发出信号。 每个队列包含多个插槽。 这允许IOP和Channel在目标队列上写入多个消息，而不会遇到CCA忙信号。 实际的队列现在由硬件系统内存构成。

    Channel communication array queues in hardware system area
    3.
    发明授权
    Channel communication array queues in hardware system area 失效
    硬件系统区域中的通道通信阵列队列

    公开(公告)号：US07437490B2

    公开(公告)日：2008-10-14

    申请号：US11139728

    申请日：2005-05-27

    申请人： Daniel F. Casper ,  John R. Flanagan ,  Paul S. Frazer ,  Kenneth J. Oakes ,  John S. Trotter

    发明人： Daniel F. Casper ,  John R. Flanagan ,  Paul S. Frazer ,  Kenneth J. Oakes ,  John S. Trotter

    IPC分类号： G06F3/00 ,  G06F13/12

    CPC分类号： G06F13/12

    摘要： A bi-directional and full duplex facility for permitting both the IO processor and the Channel to write CCA messages on their respective queues at the same time. IOP messages to the channel are stored on the TO_CHN queue and Channel messages to the IOP on the TO_IOP queue. CCA Queues replace hardware CCAs due to increasing transmission capabilities of current IO processors and Channel processors. Even though the mechanism is similar, the present invention provides some benefits in the use of signaling. The IOP does not have to signal the Channel each time it puts something on its outbound queue. Each queue contains multiple slots. This allows the IOP and Channel to write multiple messages on the targeted queue without encountering a CCA busy signal. The actual queues are now structured in hardware system memory.

    摘要翻译： 双向和全双工设备，用于允许IO处理器和通道同时在其各自的队列上写入CCA消息。 到该通道的IOP消息存储在TO_CHN队列上，并将通道消息存储到TO_IOP队列上的IOP。 由于当前IO处理器和通道处理器的传输能力不断增加，CCA队列取代硬件CCA。 即使该机制相似，本发明在使用信令方面提供了一些益处。 每当它在其出站队列上放置某些东西时，IOP都不必向Channel发出信号。 每个队列包含多个插槽。 这允许IOP和Channel在目标队列上写入多个消息，而不会遇到CCA忙信号。 实际的队列现在由硬件系统内存构成。

    Multiple I/O path selection among disparate channel paths
    4.
    发明授权
    Multiple I/O path selection among disparate channel paths 失效
    在不同的通道路径之间选择多个I / O路径

    公开(公告)号：US06973529B2

    公开(公告)日：2005-12-06

    申请号：US09966434

    申请日：2001-09-28

    申请人： Daniel F. Casper ,  Kenneth J. Oakes ,  John S. Trotter

    发明人： Daniel F. Casper ,  Kenneth J. Oakes ,  John S. Trotter

    IPC分类号： G06F13/28 ,  G06F13/00

    CPC分类号： G06F13/28

    摘要： An apparatus, method and program product for selecting paths between a main memory and I/O devices in a data processing system having a main memory for storing data, one or more I/O devices for receiving data from or sending data to the main memory, and an I/O processor (IOP) for controlling I/O operations for sending data between the main memory and the I/O devices. The data processing system includes disparate channels between the IOP and the I/O devices. The disparate channels carry data between the main memory and the I/O devices during the I/O operations. Included is a computer program executed by the IOP for assigning a path weight to selected ones of the disparate channel paths to be used in selecting the next channel path to carry data between the main memory and I/O devices. Each disparate channel type has a different set of criteria for evaluating the path weight.

    摘要翻译： 一种用于在具有用于存储数据的主存储器的数据处理系统中选择主存储器和I / O设备之间的路径的装置，方法和程序产品，用于从主存储器接收数据或向主存储器发送数据的一个或多个I / O设备 以及用于控制在主存储器和I / O设备之间发送数据的I / O操作的I / O处理器（IOP）。 数据处理系统包括IOP和I / O设备之间的不同通道。 不同的通道在I / O操作期间在主存储器和I / O设备之间传送数据。 包括由IOP执行的计算机程序，用于将路径权重分配给选择的不同通道路径，以用于选择下一个信道路径以在主存储器和I / O设备之间传送数据。 每个不同的通道类型具有用于评估路径权重的不同标准集合。

    COMMUNICATION PATH SELECTION
    5.
    发明申请
    COMMUNICATION PATH SELECTION 有权
    通信路径选择

    公开(公告)号：US20130339551A1

    公开(公告)日：2013-12-19

    申请号：US13523958

    申请日：2012-06-15

    申请人： John R. Flanagan ,  Francis Gassert ,  Kenneth J. Oakes ,  Dale F. Riedy ,  Peter Sutton ,  John S. Trotter ,  Harry M. Yudenfriend

    发明人： John R. Flanagan ,  Francis Gassert ,  Kenneth J. Oakes ,  Dale F. Riedy ,  Peter Sutton ,  John S. Trotter ,  Harry M. Yudenfriend

    IPC分类号： G06F3/00

    CPC分类号： G06F13/4022

    摘要： A computer system includes a processor configured for detecting initial command response times of a plurality of paths for transmitting signals from the processor to one or more external devices via a plurality of channels, assigning weighted values to the plurality of paths based on the detected initial command response times, and modifying a frequency at which respective paths among the plurality of paths are selected for transmitting the signals based on the weighted values assigned to the respective paths.

    摘要翻译： 计算机系统包括：处理器，被配置为检测多个路径的初始命令响应时间，用于经由多个信道将信号从处理器发送到一个或多个外部设备;基于检测到的初始命令向多个路径分配加权值 响应时间，以及修改多个路径中的相应路径被选择用于基于分配给相应路径的加权值来发送信号的频率。

    Method, system, and computer program product for timing operations of different durations in a multi-processor, multi-control block environment
    7.
    发明授权
    Method, system, and computer program product for timing operations of different durations in a multi-processor, multi-control block environment 有权
    用于在多处理器，多控制块环境中不同持续时间的定时操作的方法，系统和计算机程序产品

    公开(公告)号：US07600049B2

    公开(公告)日：2009-10-06

    申请号：US11531748

    申请日：2006-09-14

    申请人： Kenneth J. Oakes ,  John S. Trotter

    发明人： Kenneth J. Oakes ,  John S. Trotter

    IPC分类号： G06F3/00

    CPC分类号： G06F9/5011 ,  G06F3/0659 ,  G06F9/5016 ,  G06F2209/5021

    摘要： Operations in a multi-processor, multi-control block environment are timed using timing queues and instruction queues. Upon receipt of a request for a subchannel control block (SCB) to perform an operation that needs to be timed, the SCB is queued on one of multiple timing queues based on an elapsed timeout limit (ETL) of the operation. There is an ETL for each operation, and each one the multiple timing queues is associated with an ETL for completing an operation. The SCB may be placed at the bottom of the timing queue, the timing queue ordered from oldest to youngest which allows for quickly checking large numbers of SCBs without having to check every element queue and without having to dequeuing the elements from this queue. Upon receipt of a request to perform a high-priority operation, the SCB may be queued in a high priority instruction queue. The SCB may remain the timing queue to retain its order and be placed on a high priority instruction queue for retrying an operation. Upon completion of the operation or occurrence of a timeout, the SCB is dequeued. The SCB may be requeued if it was dequeued upon occurrence of a timeout. One or more timing queues may be checked for SCB operation timeouts by one or more SAPs in a round robin fashion.

    摘要翻译： 多处理器，多控制块环境中的操作使用定时队列和指令队列进行定时。 在接收到对子信道控制块（SCB）的请求以执行需要定时的操作时，SCB基于该操作的经过的超时限制（ETL）在多个定时队列中的一个上排队。 每个操作都有一个ETL，并且多个定时队列中的每一个都与ETL相关联，用于完成操作。 SCB可以放置在定时队列的底部，时序队列从最早到最晚排序，这样可以快速检查大量的SCB，而无需检查每个元素队列，而不需要从该队列中引出元素。 在接收到执行高优先级操作的请求时，SCB可以在高优先级指令队列中排队。 SCB可以保留定时队列以保持其顺序并且被放置在用于重试操作的高优先级指令队列中。 在完成操作或发生超时时，SCB出队。 如果在发生超时时出现队列，则可以重新计算SCB。 可以通过循环方式的一个或多个SAP来检查一个或多个计时队列的SCB操作超时。