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1.发明授权Signal history controlled slew-rate transmission method and bus interface transmitter 失效信号历史控制压摆率传输方式和总线接口发射机公开(公告)号：US07352211B1
公开(公告)日：2008-04-01
申请号：US11466122
申请日：2006-08-22
IPC分类号： H03K19/0175 , H03B5/22
CPC分类号： H04L25/0286 , H04L25/0272
摘要： A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.
摘要翻译： 信号历史控制的转换速率传输方法和总线接口发射机提供了一种具有低复杂度的改进的信道均衡机制。 可变转换速率前馈预加重电路根据发送信号的历史改变所施加的预加重的转换速率。 预加重电路可以由提供发射机的输出并具有不同电流值的一对电流源来实现。 控制电流源，使得在信号值变化时，提供高压摆率，并且当两个连续信号周期的信号值不变时，转换速率降低。 可以使用具有受控幅度的电流源来提供随时间变化的压摆率，并且持续地减小，直到发生另一个传输值变化。
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2.发明授权Signal history controlled slew-rate transmission method and bus interface transmitter 失效信号历史控制压摆率传输方式和总线接口发射机公开(公告)号：US07696787B2
公开(公告)日：2010-04-13
申请号：US11962093
申请日：2007-12-21
IPC分类号： H03K19/0175 , H03B5/22
CPC分类号： H04L25/0286 , H04L25/0272
摘要： A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.
摘要翻译： 信号历史控制的转换速率传输方法和总线接口发射机提供了一种具有低复杂度的改进的信道均衡机制。 可变转换速率前馈预加重电路根据发送信号的历史改变所施加的预加重的转换速率。 预加重电路可以由提供发射机的输出并具有不同电流值的一对电流源来实现。 控制电流源，使得在信号值变化时，提供高压摆率，并且当两个连续信号周期的信号值不变时，转换速率降低。 可以使用具有受控幅度的电流源来提供随时间变化的压摆率，并且持续地减小，直到发生另一个传输值变化。
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3.发明申请Signal History Controlled Slew-Rate Transmission Method and Bus Interface Transmitter 失效信号历史控制压摆率传输方法和总线接口发射机公开(公告)号：US20080061826A1
公开(公告)日：2008-03-13
申请号：US11466122
申请日：2006-08-22
IPC分类号： H03K19/0175
CPC分类号： H04L25/0286 , H04L25/0272
摘要： A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.
摘要翻译： 信号历史控制的转换速率传输方法和总线接口发射机提供了一种具有低复杂度的改进的信道均衡机制。 可变转换速率前馈预加重电路根据发送信号的历史改变所施加的预加重的转换速率。 预加重电路可以由提供发射机的输出并具有不同电流值的一对电流源来实现。 控制电流源，使得在信号值变化时，提供高压摆率，并且当两个连续信号周期的信号值不变时，转换速率降低。 可以使用具有受控幅度的电流源来提供随时间变化的压摆率，并且持续地减小，直到发生另一个传输值变化。
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公开(公告)号：US20090049339A1
公开(公告)日：2009-02-19
申请号：US11840481
申请日：2007-08-17
IPC分类号： G06F11/00
CPC分类号： G06F11/2733 , G11C5/04 , G11C29/02 , G11C29/022 , G11C29/16 , G11C29/56 , G11C2029/5602
摘要： A programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.
摘要翻译： 可编程诊断内存模块提供了内存控制器和内存子系统设计的增强的可测试性。 可编程诊断存储器模块包括用于与外部诊断系统通信的接口，并且该接口用于将命令传送到存储器模块以改变存储器模块的各种行为。 改变的行为可能是改变被写入存储器模块的数据流，以模拟错误，改变存储器模块信号的定时和/或加载，下载由存储器模块内的处理器核心执行的程序，改变驱动器的输出强度 存储器模块的信号和在模拟域中的操作，在存储器模块的端子处发出信号，例如在与存储器模块的电源连接上注入噪声。 存储器模块可以模拟多个可选择的存储器模块类型，并且可以包括完整的存储阵列以提供标准存储器模块操作。
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5.发明申请Method for Performing Memory Diagnostics Using a Programmable Diagnostic Memory Module 失效使用可编程诊断内存模块执行内存诊断的方法公开(公告)号：US20090049341A1
公开(公告)日：2009-02-19
申请号：US11840498
申请日：2007-08-17
CPC分类号： G06F11/24
摘要： A method for performing memory diagnostics using a programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.
摘要翻译： 使用可编程诊断存储器模块执行存储器诊断的方法提供了存储器控制器和存储器子系统设计的增强的可测试性。 可编程诊断存储器模块包括用于与外部诊断系统通信的接口，并且该接口用于将命令传送到存储器模块以改变存储器模块的各种行为。 改变的行为可能是改变被写入存储器模块的数据流，以模拟错误，改变存储器模块信号的定时和/或加载，下载由存储器模块内的处理器核心执行的程序，改变驱动器的输出强度 存储器模块的信号和在模拟域中的操作，在存储器模块的端子处发出信号，例如在与存储器模块的电源连接上注入噪声。 存储器模块可以模拟多个可选择的存储器模块类型，并且可以包括完整的存储阵列以提供标准存储器模块操作。
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公开(公告)号：US20080142249A1
公开(公告)日：2008-06-19
申请号：US11610470
申请日：2006-12-13
CPC分类号： H05K1/0242 , H05K3/384 , H05K3/4611 , H05K2201/09972 , Y10T29/49155
摘要： A circuit board and a method for fabricating a circuit board are provided. The circuit board includes a dielectric core comprising a first surface and a second surface and a conductive layer comprising a first surface and a second surface. The first surface of the conductive layer is coupled to the second surface of the dielectric core. A first region of the second surface of the conductive layer is smooth and a second region of the second surface of the conductive layer is rough. The first region of the second surface of the conductive layer is operable to support high speed signaling and the second region of the second surface of the conductive layer is operable to support non-high speed signaling.
摘要翻译： 提供电路板和制造电路板的方法。 该电路板包括一个包括一个第一表面和一个第二表面的电介质芯，以及一个包括第一表面和第二表面的导电层。 导电层的第一表面耦合到介质芯的第二表面。 导电层的第二表面的第一区域是光滑的，并且导电层的第二表面的第二区域是粗糙的。 导电层的第二表面的第一区可操作以支持高速信号，并且导电层的第二表面的第二区可操作以支持非高速信号。
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公开(公告)号：US07977574B2
公开(公告)日：2011-07-12
申请号：US12265407
申请日：2008-11-05
IPC分类号： H01B7/00
CPC分类号： H01B13/26 , H01B11/1025 , Y10T29/49123
摘要： Cables and methods of manufacturing cables for high speed data communications, the cable including: a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer, the inner conductors and the dielectric layers parallel with and along a longitudinal axis; and folded conductive shield material wrapped in a rotational direction along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps along and about the longitudinal axis, the conductive shield material comprising a first conductive layer and second conductive layer separated by an inner-shield dielectric layer.
摘要翻译： 用于制造用于高速数据通信的电缆的电缆和方法，所述电缆包括：被第一电介质层包围的第一内部导体和由第二电介质层包围的第二内部导体，所述内部导体和电介质层与 纵轴; 以及折叠的导电屏蔽材料沿着并围绕纵向轴线围绕内部导体和电介质层缠绕，包括围绕纵向轴线重叠的包裹物，导电屏蔽材料包括由第一导电层和第二导电层分隔的第二导电层 内屏蔽介电层。
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8.发明授权Apparatus, system, and method for dynamic phase equalization in a communication channel 有权通信信道中动态相位均衡的装置，系统和方法公开(公告)号：US07813447B2
公开(公告)日：2010-10-12
申请号：US11560257
申请日：2006-11-15
申请人： Daniel N. De Araujo , Moises Cases , Bradley D. Herrman , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham
发明人： Daniel N. De Araujo , Moises Cases , Bradley D. Herrman , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham
IPC分类号： H04L25/03
CPC分类号： H04L25/0264 , H04L25/0286
摘要： An apparatus, system, and method are disclosed for dynamic phase equalization in a communication channel. A transmitter history module stores a plurality of bits from a data stream that is transmitted through the communication channel. A transmitter detection module detects a pre-transition bit of a first value that is preceded in the data stream by at least one bit of the first value and followed by a transition bit with a second value. A driver module transmits the data stream by driving the communication channel. A transition module pre-drives the communication channel to the second voltage of the transition bit during a bit time interval of the pre-transition bit.
摘要翻译： 公开了用于通信信道中的动态相位均衡的装置，系统和方法。 发射机历史模块从通过通信信道发送的数据流存储多个比特。 发射机检测模块检测在数据流中前面的第一值的前转换比特的第一值的至少一个比特，然后跟随具有第二值的转换比特。 驾驶员模块通过驱动通信信道来发送数据流。 转换模块在预转换位的位时间间隔期间将通信通道预驱动到转换位的第二电压。
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9.发明授权Method for performing memory diagnostics using a programmable diagnostic memory module 失效使用可编程诊断存储器模块执行存储器诊断的方法公开(公告)号：US07730369B2
公开(公告)日：2010-06-01
申请号：US11840498
申请日：2007-08-17
IPC分类号： G11C29/00
CPC分类号： G06F11/24
摘要： A method for performing memory diagnostics using a programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.
摘要翻译： 使用可编程诊断存储器模块执行存储器诊断的方法提供了存储器控制器和存储器子系统设计的增强的可测试性。 可编程诊断存储器模块包括用于与外部诊断系统通信的接口，并且该接口用于将命令传送到存储器模块以改变存储器模块的各种行为。 改变的行为可能是改变被写入存储器模块的数据流，以模拟错误，改变存储器模块信号的定时和/或加载，下载由存储器模块内的处理器核心执行的程序，改变驱动器的输出强度 存储器模块的信号和在模拟域中的操作，在存储器模块的端子处发出信号，例如在与存储器模块的电源连接上注入噪声。 存储器模块可以模拟多个可选择的存储器模块类型，并且可以包括完整的存储阵列以提供标准存储器模块操作。
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公开(公告)号：US07739562B2
公开(公告)日：2010-06-15
申请号：US11840481
申请日：2007-08-17
IPC分类号： G01C29/00
CPC分类号： G06F11/2733 , G11C5/04 , G11C29/02 , G11C29/022 , G11C29/16 , G11C29/56 , G11C2029/5602
摘要： A programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.
摘要翻译： 可编程诊断内存模块提供了内存控制器和内存子系统设计的增强的可测试性。 可编程诊断存储器模块包括用于与外部诊断系统通信的接口，并且该接口用于将命令传送到存储器模块以改变存储器模块的各种行为。 改变的行为可能是改变被写入存储器模块的数据流，以模拟错误，改变存储器模块信号的定时和/或加载，下载由存储器模块内的处理器核心执行的程序，改变驱动器的输出强度 存储器模块的信号和在模拟域中的操作，在存储器模块的端子处发出信号，例如在与存储器模块的电源连接上注入噪声。 存储器模块可以模拟多个可选择的存储器模块类型，并且可以包括完整的存储阵列以提供标准存储器模块操作。
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