公开(公告)号：US08432983B2

公开(公告)日：2013-04-30

申请号：US12952164

申请日：2010-11-22

申请人： Dariush Dabiri

发明人： Dariush Dabiri

IPC分类号： H04K1/10

CPC分类号： H04B3/46 ,  H04B17/345

摘要： One or more processing units are programmed to select from among M tones in a frequency domain representation of a signal, a set of tones including at least a strongest tone (relative to background noise) and a tone adjacent thereto. From among M complex numbers in the frequency domain representation of the signal, a set of complex numbers are identified and denoted as a vector Z, corresponding to the selected set of tones. Vector Z is then multiplied with each of M columns of a matrix G which is predetermined to identify a sub-resolution maxima in Z. The M products that result from the vector multiplication of Z and G are used to determine and store in memory at least one or both of: (A) a flag indicating presence or absence of narrowband interference in the signal; and (B) an estimate of a frequency of the narrowband interference.

公开(公告)号：US08234550B2

公开(公告)日：2012-07-31

申请号：US12613627

申请日：2009-11-06

申请人： Dariush Dabiri ,  Nitin Barot

发明人： Dariush Dabiri ,  Nitin Barot

IPC分类号： H03M13/00 ,  H03M13/03

CPC分类号： H03M13/1137 ,  H03M13/1111 ,  H03M13/114 ,  H03M13/616

摘要： A decoder includes circuitry for generating bits representing received signals, and beliefs representing an associated reliability of each bit. A bit node computation block receives the bits and associated beliefs, and generates a plurality of bit node messages. A plurality of M serially-connected pipeline stages receive the bit node messages and after M decoding cycles, and generate a plurality of check node messages once per decoding cycle, wherein for each iteration cycle, each of the M serially-connected pipeline stages performs check node computations using all of J component codes, wherein each one of the M serially-connected pipeline stages performs check node computations once per decoding cycle using a single component code that is different that component codes used for all other of the M serially-connected pipeline stages, wherein J is at least as great as M, and wherein each iteration includes M decoding cycles.

摘要翻译： 解码器包括用于产生表示接收信号的比特的电路，以及表示每个比特的相关可靠性的信念。 比特节点计算块接收比特和相关联的信念，并且生成多个比特节点消息。 多个M个串行连接的流水线级接收比特节点消息，并且在M个解码周期之后，并且每解码周期生成多个校验节点消息，其中对于每个迭代周期，每个M个串行连接的流水线级执行检查 使用所有J个分量代码的节点计算，其中M个串行连接的流水线级中的每一个使用不同于用于所有其他M个串行连接的流水线的分量代码来执行每个解码周期一次的校验节点计算 其中J至少与M一样大，并且其中每个迭代包括M个解码周期。

公开(公告)号：US20120131080A1

公开(公告)日：2012-05-24

申请号：US12952193

申请日：2010-11-22

申请人： Maged F. Barsoum ,  Jinwen Xi ,  Dariush Dabiri

发明人： Maged F. Barsoum ,  Jinwen Xi ,  Dariush Dabiri

IPC分类号： G06F17/10

CPC分类号： H03H17/04 ,  H03H2218/06

摘要： Methods and systems for multi-input IIR filters with error feedback are disclosed. By using multiple-inputs to generate multiple outputs during each iteration, a multi-input IIR filter in accordance with the present invention has greatly increased throughput. Furthermore, the addition of a multi-variable error feedback unit in accordance with the present invention in a multiple-input IIR filter can greatly increase the accuracy of the multi-variable IIR Filter.

摘要翻译： 公开了具有误差反馈的多输入IIR滤波器的方法和系统。 通过在每次迭代期间通过使用多输入来产生多个输出，根据本发明的多输入IIR滤波器大大提高了吞吐量。 此外，在多输入IIR滤波器中添加根据本发明的多变量误差反馈单元可以大大提高多变量IIR滤波器的精度。

公开(公告)号：US20070211794A1

公开(公告)日：2007-09-13

申请号：US11373928

申请日：2006-03-13

申请人： Dariush Dabiri ,  Jose Tellado ,  Sandeep Gupta

发明人： Dariush Dabiri ,  Jose Tellado ,  Sandeep Gupta

IPC分类号： H04L5/16 ,  H04B3/20

CPC分类号： H04L5/1423 ,  H04B3/23

摘要： Embodiments of a method and apparatus for reducing non-linear transmit signal components of a receive signal of a transceiver signal are disclosed. The method includes the transceiver simultaneously transmitting a transmit signal, and receiving the receive signal. A non-linear replica signal of non-linear transmission signal components that are created in the transceiver by a transmit signal DAC, and imposed onto the receive signal, is generated. The non-linear replica signal is subtracted from the received signal reducing the non-linear transmission signal components imposed onto the receive signal.

摘要翻译： 公开了一种用于减少收发信机的接收信号的非线性发送信号分量的方法和装置的实施例。 该方法包括收发机同时发送发送信号，并接收接收信号。 产生通过发送信号DAC在收发器中产生且施加到接收信号上的非线性传输信号分量的非线性复制信号。 从接收到的信号中减去非线性复制信号，减少施加在接收信号上的非线性传输信号分量。

公开(公告)号：US06741644B1

公开(公告)日：2004-05-25

申请号：US09499194

申请日：2000-02-07

申请人： Hossein Dehghan ,  Ting-Yin Chen ,  Dariush Dabiri

发明人： Hossein Dehghan ,  Ting-Yin Chen ,  Dariush Dabiri

IPC分类号： H03H730

CPC分类号： H03H17/0294 ,  H03H21/0001 ,  H04L25/03878

摘要： A communications receiver and method are provided for receiving a transmitted signal from a transmission channel having a low-pass filter characteristic. The receiver includes a receiver input for coupling to the channel and a switched capacitor pre-emphasis filter coupled to the receiver input. An analog-to-digital (A/D) converter is coupled to an output of the pre-emphasis filter. An equalizer is coupled to an output of the analog-to-digital converter.

摘要翻译： 提供了一种用于从具有低通滤波器特性的传输信道接收发射信号的通信接收机和方法。 接收器包括用于耦合到通道的接收器输入端和耦合到接收器输入端的开关电容器预加重滤波器。 模数（A / D）转换器耦合到预加重滤波器的输出端。 均衡器耦合到模数转换器的输出端。

公开(公告)号：US08416719B2

公开(公告)日：2013-04-09

申请号：US12077672

申请日：2008-03-20

申请人： Dariush Dabiri

发明人： Dariush Dabiri

IPC分类号： H04B3/20

CPC分类号： H04B3/231

摘要： Embodiments of a method and apparatus for generating an estimated non-linear echo signal are disclosed. One method includes receiving a plurality of data inputs. The plurality of data inputs are partitioned into subsets. A weight vector is computed for each of the subsets. A vector of addresses to memory locations is computed for each of the subsets. Values of interpolants are accessed at the memory locations (interpolation sites) based on the vector of addresses for each of the subsets. The estimated non-linear echo signal based is calculated on the values of the interpolants and the weight vector corresponding to each subset.

公开(公告)号：US08295214B2

公开(公告)日：2012-10-23

申请号：US12765097

申请日：2010-04-22

申请人： Gaurav Chandra ,  Moshe Malkin ,  Dariush Dabiri

发明人： Gaurav Chandra ,  Moshe Malkin ,  Dariush Dabiri

IPC分类号： H04B3/20

CPC分类号： H04B3/23 ,  H04L5/1461 ,  H04M9/082

摘要： Embodiments of a method and apparatus of reducing transmit signal components of a receive signal of a transceiver are disclosed. One method includes generating a transmit signal by passing a pre-driver transmit signal through a transmit driver. An echo cancellation signal is generated by passing the pre-driver transmit signal through an echo cancellation driver. A residual echo signal is generated by passing a pre-driver residual echo cancellation signal through a residual echo cancellation driver. The transceiver simultaneously transmits the transmit signal, and receiving the receive signal. At least a portion of an echo signal of the receive signal is canceled by summing the echo cancellation signal with the receive signal. At least another portion of the cancellation echo signal of the receive signal is canceled by summing the residual echo cancellation signal with the receive signal.

摘要翻译： 公开了一种降低收发器的接收信号的发射信号分量的方法和装置的实施例。 一种方法包括通过将预驱动器发送信号通过发送驱动器来产生发送信号。 通过将预驱动器发送信号通过回波消除驱动器来产生回波消除信号。 通过将预驱动器残留回声消除信号通过残余回声消除驱动器来产生残留回波信号。 收发器同时发送发送信号，并接收接收信号。 通过将回波消除信号与接收信号相加来消除接收信号的回波信号的至少一部分。 接收信号的消除回波信号的至少另一部分通过将残差回波消除信号与接收信号相加来消除。

公开(公告)号：US20100058143A1

公开(公告)日：2010-03-04

申请号：US12613627

申请日：2009-11-06

申请人： Dariush Dabiri ,  Nitin Barot

发明人： Dariush Dabiri ,  Nitin Barot

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1137 ,  H03M13/1111 ,  H03M13/114 ,  H03M13/616

摘要： Embodiments of a method and apparatus for decoding signals are disclosed. An embodiment of a decoder includes means for generating bits representing received signals, and beliefs representing an associated reliability of each bit. A bit node computation block receives the bits and associated beliefs, and generates a plurality of bit node messages. A plurality of M serially-connected pipeline stages receive the bit node messages and after M decoding cycles, and generate a plurality of check node messages once per decoding cycle, wherein for each iteration cycle, each of the M serially-connected pipeline stages performs check node computations using all of J component codes, wherein each one of the M serially-connected pipeline stages performs check node computations once per decoding cycle using a single component code that is different that component codes used for all other of the M serially-connected pipeline stages, wherein J is at least as great as M, and wherein each iteration includes M decoding cycles.

摘要翻译： 公开了用于解码信号的方法和装置的实施例。 解码器的实施例包括用于产生表示接收信号的比特的装置，以及表示每个比特的相关可靠性的信念。 比特节点计算块接收比特和相关联的信念，并且生成多个比特节点消息。 多个M个串行连接的流水线级接收比特节点消息，并且在M个解码周期之后，并且每解码周期生成多个校验节点消息，其中对于每个迭代周期，每个M个串行连接的流水线级执行检查 使用所有J个分量代码的节点计算，其中M个串行连接的流水线级中的每一个使用不同于用于所有其他M个串行连接的流水线的分量代码来执行每个解码周期一次的校验节点计算 其中J至少与M一样大，并且其中每个迭代包括M个解码周期。

公开(公告)号：US20060047857A1

公开(公告)日：2006-03-02

申请号：US10926699

申请日：2004-08-26

申请人： Dariush Dabiri ,  Jose Tellado

发明人： Dariush Dabiri ,  Jose Tellado

IPC分类号： G06F15/16

CPC分类号： H03M13/37 ,  H04L1/0045 ,  H04L1/0057

摘要： Embodiments of a method and apparatus for decoding an Ethernet signal are disclosed. The method includes receiving an Ethernet bit stream. The bit stream is at least one of low-complexity decoded or high-complexity decoded. If the bit stream fails a low-complexity decoding test, then the bit stream is high-complexity decoded. The low-complexity decoding and high complexity decoding are iteratively repeated until the bit stream passes the low-complexity decoding test.

摘要翻译： 公开了用于解码以太网信号的方法和装置的实施例。 该方法包括接收以太网比特流。 比特流是低复杂度解码或高复杂度解码中的至少一个。 如果比特流失败了低复杂度的解码测试，则比特流是高复杂度的解码。 迭代重复低复杂度解码和高复杂度解码，直到比特流通过低复杂度解码测试。

公开(公告)号：US06549591B1

公开(公告)日：2003-04-15

申请号：US09712403

申请日：2000-11-13

申请人： Christopher Keate ,  Ravi Bhaskaran ,  Dariush Dabiri

发明人： Christopher Keate ,  Ravi Bhaskaran ,  Dariush Dabiri

IPC分类号： H04L2508

CPC分类号： H04B1/123

摘要： Digital interference rejection of a signal is accomplished by first converting the signal to digital. Then a second signal is generated and mixed with the first signal. This combined signal is then filtered. The signal can then be scaled as needed, resulting in a finely tuned, interference free signal.

摘要翻译： 信号的数字干扰抑制是通过首先将信号转换为数字来实现的。 然后产生第二信号并与第一信号混合。 然后对该组合信号进行滤波。 然后可以根据需要对信号进行缩放，从而产生微调，无干扰的信号。