公开(公告)号：US06549591B1

公开(公告)日：2003-04-15

申请号：US09712403

申请日：2000-11-13

Applicant: Christopher Keate ,  Ravi Bhaskaran ,  Dariush Dabiri

Inventor： Christopher Keate ,  Ravi Bhaskaran ,  Dariush Dabiri

IPC: H04L2508

CPC classification number: H04B1/123

Abstract: Digital interference rejection of a signal is accomplished by first converting the signal to digital. Then a second signal is generated and mixed with the first signal. This combined signal is then filtered. The signal can then be scaled as needed, resulting in a finely tuned, interference free signal.

Abstract translation: 信号的数字干扰抑制是通过首先将信号转换为数字来实现的。 然后产生第二信号并与第一信号混合。 然后对该组合信号进行滤波。 然后可以根据需要对信号进行缩放，从而产生微调，无干扰的信号。

公开(公告)号：US6167098A

公开(公告)日：2000-12-26

申请号：US8109

申请日：1998-01-16

Applicant: Christopher Keate ,  Ravi Bhaskaran ,  Dariush Dabiri

Inventor： Christopher Keate ,  Ravi Bhaskaran ,  Dariush Dabiri

IPC: H04B1/12 ,  H04L25/08 ,  H04L25/06

CPC classification number: H04B1/123

Abstract: Digital interference rejection of a signal is accomplished by first converting the signal to digital. Then a second signal is generated and mixed with the first signal. This combined signal is then filtered. The signal can then be scaled as needed, resulting in a finely tuned, interference free signal.

公开(公告)号：US06665355B1

公开(公告)日：2003-12-16

申请号：US09391973

申请日：1999-09-08

Applicant: Ting-Yin Chen ,  Ravi Bhaskaran ,  Christopher Keate ,  Kedar D. Shirali

Inventor： Ting-Yin Chen ,  Ravi Bhaskaran ,  Christopher Keate ,  Kedar D. Shirali

IPC: H03D124

CPC classification number: H03D1/24

Abstract: An inexpensive synchronous detection module is disclosed for a sideband signal receiver that provides for flexibility in design of the tuner. The detection module is adaptable to detection of upper or lower sideband signals. One embodiment includes an analog-to-digital converter, a Hilbert transform filter, a sideband selection switch, a complex multiplier, a carrier recovery. loop, a matched filter, and a decimator. The analog-to-digital converter oversamples an intermediate frequency (IF) signal from the tuner, and the Hilbert transform filter generates a Hilbert transform of the digital IF signal. An analytic IF signal can be generated from the digital IF signal by multiplying the Hilbert transform of the digital IF signal by j(=sqrt(−1)), and adding the resulting imaginary-valued signal to the digital IF signal. The sideband selection switch can “flip” the analytic IF signal by inverting the imaginary-valued signal. The complex multiplier multiplies the analytic IF signal by a complex-value sinusoid to shift the analytic IF signal to baseband. The resulting analytic baseband signal is match filtered and decimated to form a baseband double sideband signal with one sample per symbol period. The carrier recovery loop operates on the imaginary part of the analytic baseband signal to generate the complex sinusoid that shifts the analytic IF signal to baseband.

Abstract translation: 公开了一种边缘信号接收机的便宜的同步检测模块，其提供了调谐器设计的灵活性。 检测模块适用于检测上或下边带信号。 一个实施例包括模数转换器，希尔伯特变换滤波器，边带选择开关，复数乘法器，载波恢复。 循环，匹配滤波器和抽取器。 模数转换器从调谐器中抽取中频（IF）信号，希尔伯特变换滤波器产生数字IF信号的希尔伯特变换。 通过将数字IF信号的希尔伯特变换乘以j（= sqrt（-1）），并将产生的虚值信号与数字IF信号相加，可以从数字IF信号产生分析IF信号。 边带选择开关可以通过反相虚值信号来“翻转”分析IF信号。 复数乘法器将分析的IF信号乘以复数值正弦波，以将分析的IF信号移位到基带。 所得到的分析基带信号被匹配滤波和抽取以形成基带双边带信号，每个符号周期具有一个样本。 载波恢复循环在分析基带信号的虚部上运行，以产生将分析IF信号转换为基带的复数正弦波。

公开(公告)号：US5953636A

公开(公告)日：1999-09-14

申请号：US741269

申请日：1996-10-30

Applicant: Christopher Keate ,  Daniel Luthi

Inventor： Christopher Keate ,  Daniel Luthi

IPC: H04H40/90 ,  H04L1/00 ,  H04H1/00

CPC classification number: H04H40/90 ,  H04L1/0054 ,  H04L1/0057 ,  H04L1/0059 ,  H04L1/0065 ,  H04L1/0068 ,  H04L1/0071

Abstract: The present invention concerns a DBS receiver which serves to combine the functions of variable rate demodulation, convolutional decoding, de-interleaving and block decoding. The demodulation stage includes a novel circuit for clock synchronization. By combining the functions of these components this device provides a higher level of utility as measured in terms of reliability, simplicity, flexibility, cost effectiveness, and integration of board layout while maintaining optimum-quality signal processing.

Abstract translation: 本发明涉及一种DBS接收机，其用于组合可变速率解调，卷积解码，去交织和块解码的功能。 解调级包括用于时钟同步的新型电路。 通过结合这些组件的功能，该装置在可靠性，简单性，灵活性，成本效益和电路板布局集成方面提供了更高水平的实用性，同时保持最优质量的信号处理。

公开(公告)号：US5819157A

公开(公告)日：1998-10-06

申请号：US878354

申请日：1997-06-18

Applicant: Nadav Ben-Efraim ,  Christopher Keate

Inventor： Nadav Ben-Efraim ,  Christopher Keate

IPC: H04B1/16 ,  H03J7/06 ,  H04B1/30 ,  H04H40/90 ,  H04N5/21 ,  H04N5/44 ,  H04N5/455 ,  H04N7/20

CPC classification number: H04H40/90 ,  H03J7/065 ,  H04N21/426 ,  H04N21/6143 ,  H04N5/211 ,  H04N5/455 ,  H04N7/20 ,  H04B1/30 ,  H04N5/4401

Abstract: An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip has reduced-power features which allow the incorporation of an on-chip voltage regulator. The tuner chip is a direct conversion tuner with on-chip tuning frequency generation and reduced power interface signals. The on-chip voltage regulator provides a constant power supply for nonlinear components of the tuner and frequency generation circuitry to minimize phase noise. Broadly speaking, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip includes an on-chip voltage regulator, in addition to a tuning oscillator, a charge pump, a downconverter, and a lowpass filter. The on-chip voltage regulator is operable to provide a stable power supply to the tuning oscillator and the charge pump. The tuning oscillator is coupled to a tank circuit having an adjustable resonance frequency, and the charge pump is coupled to the tank circuit to control the resonance frequency. The downconverter receives a tuning frequency provided by the tuning oscillator, receives a receive signal, and combines the tuning frequency signal with the receive signal to produce a product signal. The lowpass filter acts to convert the product signal into a baseband signal, which may then be provided as a differential output signal.

Abstract translation: 具有调谐器芯片和解调器/解码器芯片的改进的DBS接收机前端架构。 调谐器芯片具有降低功率特征，其允许并入片上电压调节器。 调谐器芯片是具有片上调谐频率生成和降低的电源接口信号的直接转换调谐器。 片上稳压器为调谐器和频率发生电路的非线性元件提供恒定的电源，以最小化相位噪声。 广义而言，本发明涉及一种DBS接收器前端，其包括调谐器芯片和解调器/解码器芯片。 除了调谐振荡器，电荷泵，下变频器和低通滤波器之外，调谐器芯片还包括片上稳压器。 片上稳压器可操作以向调谐振荡器和电荷泵提供稳定的电源。 调谐振荡器耦合到具有可调节谐振频率的振荡电路，并且电荷泵耦合到储能电路以控制谐振频率。 下变频器接收由调谐振荡器提供的调谐频率，接收接收信号，并将调谐频率信号与接收信号组合以产生乘积信号。 低通滤波器用于将产品信号转换为基带信号，然后可将其作为差分输出信号提供。

公开(公告)号：US6134282A

公开(公告)日：2000-10-17

申请号：US878329

申请日：1997-06-18

Applicant: Nadav Ben-Efraim ,  Christopher Keate

Inventor： Nadav Ben-Efraim ,  Christopher Keate

IPC: H04B1/26 ,  H03J3/08 ,  H03J7/06 ,  H03J7/08 ,  H04B1/10 ,  H04B1/16 ,  H04B15/04 ,  H04H40/90

CPC classification number: H04H40/90 ,  H03J3/08 ,  H03J7/065 ,  H03J7/08 ,  H04B1/1027 ,  H04B15/04 ,  H04B2001/1054 ,  H04B2215/064

Abstract: An improved satellite receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip includes a lowpass filter having a configurable cutoff frequency, and the tuner chip uses a frequency signal to provide accurate adjustment of the cutoff frequency. A clock signal having a clock frequency is converted into a control voltage which determines the cutoff frequency of the lowpass filter. Consequently, the cutoff frequency may be increased by increasing the clock frequency, or decreased by decreasing the clock frequency. This configuration provides for improved cutoff frequency control in the presence of signal interference.

Abstract translation: 具有调谐器芯片和解调器/解码器芯片的改进的卫星接收机前端架构。 调谐器芯片包括具有可配置截止频率的低通滤波器，并且调谐器芯片使用频率信号来提供对截止频率的精确调整。 具有时钟频率的时钟信号被转换成确定低通滤波器的截止频率的控制电压。 因此，可以通过增加时钟频率来增加截止频率，或者通过降低时钟频率来减小截止频率。 该配置提供了在存在信号干扰的情况下改进的截止频率控制。

公开(公告)号：US5955783A

公开(公告)日：1999-09-21

申请号：US878333

申请日：1997-06-18

Applicant: Nadav Ben-Efraim ,  Christopher Keate

Inventor： Nadav Ben-Efraim ,  Christopher Keate

IPC: H01L23/28 ,  H03D3/00 ,  H03D7/16 ,  H04B1/08 ,  H04B1/30 ,  H04B15/00 ,  H04H40/90 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52

CPC classification number: H04H40/90 ,  H03D3/007 ,  H03D7/166 ,  H04B1/30

Abstract: A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip converts a receive signal to a baseband signal using a tuning frequency signal generated from a tank circuit. The design of a package for the tuner chip maximally spaces the pins associated with high frequency signals by placing them on opposite sides of the chip (in the case of two high frequency signal sources) or (in the case of three high frequency signal sources) in a triangle formation with widely spaced vertices wherein at least two of the pins are adjacent to corners of the package. For two or more high frequency signal sources, a good determination of pin locations can be determined according to the formula P.sub.i =C+i.multidot..left brkt-bot.N/M.right brkt-bot., i=1, . . . , M, where P.sub.i are the pin numbers, N is a total number of pins around the perimeter of the package, M is a total number of the high frequency signal sources, and C is an offset number. Where a high frequency signal source has more than one associated pin, one pin number is found from the above formula, and the associated pins are placed on adjacent pins.

Abstract translation: DBS接收机前端，包括调谐器芯片和解调器/解码器芯片。 调谐器芯片使用从电路产生的调谐频率信号将接收信号转换为基带信号。 用于调谐器芯片的封装的设计通过将与高频信号相关联的引脚放置在芯片的相对侧（在两个高频信号源的情况下）或（在三个高频信号源的情况下） 在具有广泛间隔的顶点的三角形形状中，其中至少两个销与包装的角相邻。 对于两个或更多个高频信号源，可以根据公式Pi = C + ix + 537 N / M + 540，i = 1来确定引脚位置的良好确定。 。 。 ，M，其中Pi是引脚号，N是封装周边周围的引脚总数，M是高频信号源的总数，C是偏移号。 在高频信号源具有多于一个的相关引脚的情况下，从上述公式可以看到一个引脚号，并将相应的引脚放置在相邻引脚上。

公开(公告)号：US5930688A

公开(公告)日：1999-07-27

申请号：US862156

申请日：1992-04-02

Applicant: Franklin W. Floyd ,  Christopher Keate

Inventor： Franklin W. Floyd ,  Christopher Keate

IPC: H04B1/04

CPC classification number: H04B1/0475

Abstract: An apparatus and method for suppressing intermodulation noise in a radio frequency power amplifier. Intermodulation noise suppression is achieved by use of an amplitude limiter connected to the signal source and a shaping filter connected between the amplitude limiter and the power amplifier. The shaping filter may be a band-stop notch filter which attenuates intermodulation noise in a selected radio band or a bandpass filter which attenuates all out-of-band intermodulation noise. The intermodulation noise suppression of this invention causes the signal entering the power amplifier to be characterized by (1) a low peak-to-average envelope distribution and (2) low spectral content in the radio frequency bands to be protected.

Abstract translation: 一种用于抑制射频功率放大器中的互调噪声的装置和方法。 通过使用连接到信号源的限幅器和连接在幅度限制器和功率放大器之间的整形滤波器来实现互调噪声抑制。 整形滤波器可以是衰减所选无线电频带中的互调噪声的带阻陷波滤波器或衰减所有带外互调噪声的带通滤波器。 本发明的互调噪声抑制使得进入功率放大器的信号的特征在于（1）低峰值平均包络分布和（2）待保护的无线电频带中的低频谱含量。

公开(公告)号：US6091931A

公开(公告)日：2000-07-18

申请号：US878328

申请日：1997-06-18

Applicant: Nadav Ben-Efraim ,  Christopher Keate

Inventor： Nadav Ben-Efraim ,  Christopher Keate

IPC: H04B1/26 ,  H03D7/16 ,  H03J1/00 ,  H03J7/06 ,  H04B1/16 ,  H04N7/20

CPC classification number: H03J1/0008 ,  H03D7/166 ,  H03J7/065 ,  H04N7/20

Abstract: An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip and the demodulator/decoder chip each include portions of a digital tuning frequency synthesizer. The frequency synthesizer comprises one or more digital counters which are implemented on the demodulator/decoder chip, and an oscillator which is implemented on the tuner chip. This advantageously avoids digital noise interference with the tuner chip while providing a reduced part count. Briefly, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip which cooperate to perform a frequency synthesis function. The tuner chip has a tuning oscillator coupled to a tank circuit having an adjustable resonance frequency, and a downconverter coupled to receive a tuning frequency signal provided by the tuning oscillator. The demodulator/decoder chip has a programmable counter configured to count cycles of the tuning frequency to provide a frequency-divided signal to a phase detector. The phase detector compares the frequency-divided signal to a reference frequency, and is coupled to adjust the resonance frequency of the tank circuit to cause the tuning frequency to have a frequency which is a multiple of the resonance frequency. The demodulator/decoder chip also has a decoder which receives the baseband signal and converts it to a decoded signal.

Abstract translation: 具有调谐器芯片和解调器/解码器芯片的改进的DBS接收机前端架构。 调谐器芯片和解调器/解码器芯片各自包括数字调谐频率合成器的部分。 频率合成器包括在解调器/解码器芯片上实现的一个或多个数字计数器，以及在调谐器芯片上实现的振荡器。 这有利地避免了与调谐器芯片的数字噪声干扰，同时提供减少的部件数量。 简而言之，本发明涉及一种DBS接收器前端，其包括协调以执行频率合成功能的调谐器芯片和解调器/解码器芯片。 调谐器芯片具有耦合到具有可调谐谐振频率的振荡电路的调谐振荡器，以及耦合以接收由调谐振荡器提供的调谐频率信号的下变频器。 解调器/解码器芯片具有可编程计数器，其被配置为对调谐频率的周期进行计数以向相位检测器提供分频信号。 相位检测器将分频信号与参考频率进行比较，并且耦合以调节振荡电路的谐振频率，以使调谐频率具有作为谐振频率的倍数的频率。 解调器/解码器芯片还具有接收基带信号并将其转换为解码信号的解码器。

公开(公告)号：US5835165A

公开(公告)日：1998-11-10

申请号：US476434

申请日：1995-06-07

Applicant: Christopher Keate ,  Nadav Ben-Efraim

Inventor： Christopher Keate ,  Nadav Ben-Efraim

IPC: H03M13/29 ,  H04L1/00 ,  H04N7/66 ,  H04N7/64

CPC classification number: H04L1/0057 ,  H03M13/29 ,  H04L1/0054 ,  H04L1/0065 ,  H04L1/0068 ,  H04L1/0071

Abstract: A concatenated three layer Viterbi, Reed-Solomon/Deinterleaver and Descrambler forward error correction decoder may be utilized in digital video and audio systems, and for direct broadcast satellite applications. The digital signal may be a compressed video and audio signal transmitted from a direct broadcast satellite. Acquisition for three layers of synchronization are required, but once all three layers are in-sync, down stream data synchronization monitoring will suffice so that upstream synchronization monitoring can be disabled thus improving system robustness to noise bursts and false synchronization on false sync bytes generated at the transmission encoder during non-changing data signal conditions.

Abstract translation: 连续的三层维特比，里德 - 所罗门/去交织器和解扰器前向纠错解码器可用于数字视频和音频系统以及用于直接广播卫星应用。 数字信号可以是从直接广播卫星发送的压缩视频和音频信号。 需要采集三层同步，但是一旦所有三个层同步，则下行流数据同步监视就足够了，从而可以禁止上行同步监视，从而提高系统对噪声突发的鲁棒性，并在 传输编码器在不变数据信号条件下。