公开(公告)号：US5193158A

公开(公告)日：1993-03-09

申请号：US780527

申请日：1991-10-18

申请人： Daryl F. Kinney ,  Anthony N. Drogaris ,  Christopher H. Mills ,  Michael Kahaiyan ,  John Manton

发明人： Daryl F. Kinney ,  Anthony N. Drogaris ,  Christopher H. Mills ,  Michael Kahaiyan ,  John Manton

IPC分类号： G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/3863

摘要： Method and apparatus for sequentially executing a plurality of pipelined instruction words of a program in which each instruction has independently selectable execution cycle count latencies. After the occurrence of an exception, instructions are identified which began after the instruction that caused the exception, and which have completed execution before execution of the exception provoking instruction was inhibited. Detection of an exception causes the processor to inhibit further execution of the exception provoking instruction. Pending instructions, which have yet to complete their execution prior to the inhibition of the exception provoking instruction, are similarly inhibited from further execution. Subsequently, the exception is serviced and the exception inducing instruction is restarted for re-execution in the processor. Pending instructions are subsequently re-executed in the sequence of their occurrence at the time the exception provoking instruction caused the processor to inhibit further instruction execution. Completed instructions are not re-executed. Applicable to computing systems having a plurality of processors, of either the same or different type such as floating point and integer processors, the method and apparatus inhibits all such further execution of plural processors upon the detection of an exception in one of the processors. In processors other than the processors serving the exception, no-op instructions are executed until the processor servicing the exception causes pending instructions to be re-executed, at which time the other processors also re-execute instructions which were pending at the time further execution of the instructions was inhibited.

摘要翻译： 用于顺序地执行程序的多个流水线指令字的方法和装置，其中每个指令具有独立可选的执行周期计数延迟。 在发生异常之后，在引发异常的指令之后，在执行异常发起指令之前已经完成执行的指令被禁止的指令被识别。 检测异常会导致处理器禁止进一步执行异常发起指令。 在禁止异常激发指令之前还没有完成其执行的待处理指令同样被禁止进一步执行。 随后，异常被处理并且重新启动异常诱导指令以在处理器中重新执行。 随后的指令随后在异常发出指令引起处理器禁止进一步指令执行时按其发生顺序重新执行。 完成的指令不会重新执行。 适用于具有多个相同或不同类型的处理器（如浮点和整数处理器）的计算系统，所述方法和装置在检测到处理器之一中的异常时，禁止所有进一步执行多个处理器。 在服务于异常的处理器之外的处理器中，执行无操作指令，直到处理异常的处理器导致待执行的指令被重新执行，此时其他处理器还重新执行在进一步执行时待处理的指令 的说明被禁止。

公开(公告)号：US5051885A

公开(公告)日：1991-09-24

申请号：US255105

申请日：1988-10-07

申请人： John S. Yates, Jr. ,  Stephen J. Ciavaglia ,  John Manton ,  Michael Kahaiyan ,  Richard G. Bahr ,  Barry J. Flahive

发明人： John S. Yates, Jr. ,  Stephen J. Ciavaglia ,  John Manton ,  Michael Kahaiyan ,  Richard G. Bahr ,  Barry J. Flahive

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F15/16

CPC分类号： G06F9/3889 ,  G06F9/30149 ,  G06F9/321 ,  G06F9/3814 ,  G06F9/3816 ,  G06F9/3853 ,  G06F9/3885

摘要： Apparatus and method for concurrent dispatch of instruction words which selectively comprise instruction components which are separately and substantially simultaneously received by distinct floating point and integer functional units. The instruction words are powers of 2 in length, (measured in terms of the smallest machine addressable unit) typically a 4 byte longword and an 8 byte quadword aligned to the natural boundaries also corresponding to powers of 2. To provide maximum operating efficiency, each functional (or processing) unit executes a component of an instruction word during an execution cycle. The type and length of the instruction word are indicated by one of the bit fields of the instruction word, which permits the apparatus to properly detect, store and transfer the instruction word to the appropriate functional unit. The invention combines the encoding efficiency of variable length instruction combined combined with the enhanced processing speed of simultaneous operation of all available functional units, to provide the execution efficiency of systems with a single instruction length.