公开(公告)号：US4755936A

公开(公告)日：1988-07-05

申请号：US823805

申请日：1986-01-29

申请人： Robert E. Stewart ,  Barry J. Flahive ,  James B. Keller

发明人： Robert E. Stewart ,  Barry J. Flahive ,  James B. Keller

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0855

摘要： A cache memory unit is disclosed in which, in response to the application of a write command, the write operation is performed in two system clock cycles. During the first clock cycle, the data signal group is stored in a temporary storage unit while a determination is made if the address signal group associated with the data signal group is present in the cache memory unit. When the address signal group is present, the data signal group is stored in the cache memory unit during the next application of a write command to the cache memory unit. If a read command is applied to the cache memory unit involving the data signal group stored in the temporary storage unit, then this data signal group is transferred to the central processing unit in response to the read command. Instead of performing the storage into the cache memory unit as a result of the next write command, the storage of the data signal in the cache memory unit can occur during any free cycle.

摘要翻译： 公开了一种高速缓冲存储器单元，其中响应于写入命令的应用，在两个系统时钟周期中执行写入操作。 在第一时钟周期期间，数据信号组存储在临时存储单元中，同时确定与数据信号组相关联的地址信号组是否存在于高速缓冲存储器单元中。 当存在地址信号组时，在下一次向高速缓冲存储器单元施加写入命令时，将数据信号组存储在高速缓冲存储器单元中。 如果读取命令被应用于存储在临时存储单元中的数据信号组的高速缓冲存储器单元，则该数据信号组被响应于读取命令传送到中央处理单元。 作为下一个写入命令的结果，代替执行到高速缓冲存储器单元的存储，数据信号在高速缓冲存储器单元中的存储可以在任何空闲周期期间发生。

公开(公告)号：US4290133A

公开(公告)日：1981-09-15

申请号：US954604

申请日：1978-10-25

申请人： Robert E. Stewart ,  Barry J. Flahive ,  David Potter

发明人： Robert E. Stewart ,  Barry J. Flahive ,  David Potter

IPC分类号： G06F13/378 ,  G06F13/42 ,  H04J3/08

CPC分类号： G06F13/378 ,  G06F13/4217

摘要： A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus, and each nexus in the system can communicate with other nexuses. A central clocking circuit generates timing signals that control such communications on a synchronous basis. The clocking circuit includes oscillator, control and sequencing circuits that produce phase and clocking signals that are coupled to each nexus. Each nexus contains receivers and decoders for converting the phase and clocking signals into a sequence of internal timing signals that synchronizes the operation of the nexus to transfers among the nexuses.

摘要翻译： 数字数据处理系统，包括构成系统的各种元件的互连。 连接到互连的每个元素称为连接，系统中的每个连接可以与其他的nexus通信。 中央时钟电路产生在同步基础上控制这种通信的定时信号。 时钟电路包括振荡器，控制和排序电路，其产生耦合到每个连接点的相位和时钟信号。 每个连接器包含用于将相位和时钟信号转换成内部定时信号的序列的接收器和解码器，其将该连接的操作与该互连之间的传输同步。

公开(公告)号：US5167022A

公开(公告)日：1992-11-24

申请号：US552341

申请日：1990-07-16

申请人： Richard G. Bahr ,  Andrew Milia ,  Barry J. Flahive

发明人： Richard G. Bahr ,  Andrew Milia ,  Barry J. Flahive

IPC分类号： G06F13/374 ,  G06F15/17

CPC分类号： G06F13/374 ,  G06F15/17

摘要： A method and apparatus for granting, to a select processor in a multiprocessor computing system, exclusive access to a bus for issuance of address, data and command signals thereover, wherein each processor includes bus lock request and bus lock assert elements which provide corresponding bus request and bus hold signals which are recognized by corresponding elements included in other processors connected to the bus. The bus lock according to the present invention assures the processor having lock status of privacy on the bus necessary to complete a specified operation without interruption from the other processors.

摘要翻译： 一种用于向多处理器计算系统中的选择处理器授予对总线的独占访问的方法和装置，用于在其上发布地址，数据和命令信号，其中每个处理器包括总线锁定请求和总线锁定断言元件，其提供相应的总线请求 以及由连接到总线的其他处理器中包括的相应元件识别的总线保持信号。 根据本发明的总线锁确保处理器在总线上具有完成指定操作所必需的锁定状态，而不会与其他处理器中断。

公开(公告)号：US5051885A

公开(公告)日：1991-09-24

申请号：US255105

申请日：1988-10-07

申请人： John S. Yates, Jr. ,  Stephen J. Ciavaglia ,  John Manton ,  Michael Kahaiyan ,  Richard G. Bahr ,  Barry J. Flahive

发明人： John S. Yates, Jr. ,  Stephen J. Ciavaglia ,  John Manton ,  Michael Kahaiyan ,  Richard G. Bahr ,  Barry J. Flahive

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F15/16

CPC分类号： G06F9/3889 ,  G06F9/30149 ,  G06F9/321 ,  G06F9/3814 ,  G06F9/3816 ,  G06F9/3853 ,  G06F9/3885

摘要： Apparatus and method for concurrent dispatch of instruction words which selectively comprise instruction components which are separately and substantially simultaneously received by distinct floating point and integer functional units. The instruction words are powers of 2 in length, (measured in terms of the smallest machine addressable unit) typically a 4 byte longword and an 8 byte quadword aligned to the natural boundaries also corresponding to powers of 2. To provide maximum operating efficiency, each functional (or processing) unit executes a component of an instruction word during an execution cycle. The type and length of the instruction word are indicated by one of the bit fields of the instruction word, which permits the apparatus to properly detect, store and transfer the instruction word to the appropriate functional unit. The invention combines the encoding efficiency of variable length instruction combined combined with the enhanced processing speed of simultaneous operation of all available functional units, to provide the execution efficiency of systems with a single instruction length.

公开(公告)号：US06286095B1

公开(公告)日：2001-09-04

申请号：US08533878

申请日：1995-09-26

申请人： Dale C. Morris ,  Barry J. Flahive ,  Michael L. Ziegler ,  Jerome C. Huck ,  Stephen G. Burger ,  Ruby B. L. Lee ,  Bernard L. Stumpf ,  Jeff Kurtze

发明人： Dale C. Morris ,  Barry J. Flahive ,  Michael L. Ziegler ,  Jerome C. Huck ,  Stephen G. Burger ,  Ruby B. L. Lee ,  Bernard L. Stumpf ,  Jeff Kurtze

IPC分类号： G06F1314

CPC分类号： G06F9/3834 ,  G06F9/30043 ,  G06F9/30087

摘要： A computer apparatus incorporating special instructions to force load and store operations to execute in program order. The present invention provides a new and novel store instruction that is suspended until all prior store instructions have been completed by an associated CPU. Also, a new load instruction is provided which blocks any subsequent load instructions from executing until this load instruction has been completed by an associated CPU. These instructions allow for high efficiency computer systems to be implemented which optimize instruction throughput by executing subsequent instructions while waiting for a prior instruction to complete.

摘要翻译： 一种包含强制加载和存储操作的特殊指令的计算机设备，以程序顺序执行。 本发明提供了一种新的和新颖的存储指令，直到所有先前存储指令已经被相关联的CPU完成为止。 此外，提供了新的加载指令，其阻止任何后续的加载指令执行，直到该加载指令已由相关联的CPU完成。 这些指令允许实现高效率的计算机系统，其通过在等待先前的指令完成的同时执行后续指令来优化指令吞吐量。

公开(公告)号：US6079012A

公开(公告)日：2000-06-20

申请号：US968923

申请日：1997-11-06

申请人： Dale C. Morris ,  Bernard L. Stumpf ,  Barry J. Flahive ,  Jeffrey D. Kurtze ,  Stephen G. Burger ,  Ruby B. L. Lee ,  William R. Bryg

发明人： Dale C. Morris ,  Bernard L. Stumpf ,  Barry J. Flahive ,  Jeffrey D. Kurtze ,  Stephen G. Burger ,  Ruby B. L. Lee ,  William R. Bryg

IPC分类号： G06F15/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F15/177 ,  G06F15/163

CPC分类号： G06F9/52 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/522

摘要： A computer apparatus which detects a store or load operation into or from a shared memory page by a program that does not provide for synchronization when executed by a CPU that completes instructions out of program order. After the store or load is detected, the CPU explicitly orders operations into the shared memory page. Store operations are ordered such that no new store into the shared memory page is performed until all prior store operations into the shared memory page are complete. Also, load operations are ordered such that load operations from the shared memory page are performed in program order. This ordering is achieved by maintaining a process bit and a memory attribute bit associated with a shared memory page. When both bits are true, all load or store operations referencing the shared memory page are ordered.

摘要翻译： 一种计算机装置，其通过程序执行存储或加载操作，所述程序在由程序顺序完成指令的CPU执行时不提供同步。 检测到存储或加载后，CPU会将操作明确地命令到共享内存页面中。 存储操作被排序，使得在共享存储器页面中的所有先前的存储操作完成之前，不执行在共享存储器页面中的新存储。 此外，加载操作被排序，使得来自共享存储器页面的加载操作以程序顺序执行。 该排序通过维护与共享存储器页相关联的进程位和存储器属性位来实现。 当两个位都为真时，将对所有引用共享存储器页面的加载或存储操作进行排序。

公开(公告)号：US5175829A

公开(公告)日：1992-12-29

申请号：US262495

申请日：1988-10-25

申请人： Bernard Stumpf ,  George M. Stabler ,  Richard G. Bahr ,  Stephen J. Ciavaglia ,  Barry J. Flahive ,  Hugh Lauer

发明人： Bernard Stumpf ,  George M. Stabler ,  Richard G. Bahr ,  Stephen J. Ciavaglia ,  Barry J. Flahive ,  Hugh Lauer

IPC分类号： G06F15/16 ,  G06F9/52 ,  G06F13/374 ,  G06F15/17 ,  G06F15/177

CPC分类号： G06F13/374 ,  G06F15/17

摘要： A computer system having a plurality of processors sharing common memory and data bus structures and operable to perform atomic operations which comprise several instruction actions, wherein the processor performing the atomic operation prevents memory access interruptions by other processors by locking out other processors during the atomic operation. The system bus includes signal paths accommodating bus lock request and bus lock signals which are provided and received by each processor, which signals are initiated by specific bus lock and lock release instructions added to each processor instruction set.

公开(公告)号：US4449183A

公开(公告)日：1984-05-15

申请号：US310825

申请日：1981-10-13

申请人： Barry J. Flahive ,  John J. Grady, III ,  Peter J. Rado

发明人： Barry J. Flahive ,  John J. Grady, III ,  Peter J. Rado

IPC分类号： G06F13/18 ,  G06F13/364 ,  G06F15/167 ,  G06F13/00

CPC分类号： G06F15/167 ,  G06F13/18 ,  G06F13/364

摘要： An arbitration network for use in a data multiprocessing system that includes a functional unit, such as a memory module, that is shared by several requestor devices, such as data processors, wherein access is granted to the shared functional unit through a common data bus on a rotating priority basis and wherein the arbitration cycle of the functional unit for determining priorities of the requestor devices is performed near the end of each operational cycle of the functional unit so that the next requestor device initiates its operational cycle immediately succeeding a current operational cycle then transacting thereby to minimize idle bus periods which would otherwise occur during arbitration cycle sequencing. When the bus is idle and only one request for access is made, the arbitration network foregoes the complete arbitration cycle and issues the grant to the requesting device thereby providing an earlier initiation of the data transfer cycle of the functional unit.

摘要翻译： 一种在数据多处理系统中使用的仲裁网络，其包括诸如数据处理器之类的多个请求者设备共享的诸如存储器模块的功能单元，其中通过公共数据总线向共享功能单元授予访问 旋转优先级基础，并且其中用于确定请求者设备的优先级的功能单元的仲裁周期在功能单元的每个操作周期结束时执行，使得下一个请求者设备在当前操作周期之后立即启动其操作周期 从而最小化在仲裁循环排序期间会发生的空闲总线周期。 当总线空闲并且只有一个请求访问时，仲裁网络放弃完整的仲裁周期，并向授权设备发放授权，从而提供功能单元的数据传输周期的较早启动。